Runtime Implementation Research Articles

Verification of Control System Runtime Using an Executable Semantic Model

The paper outlines a methodology for validating the accuracy of a control system’s runtime implementation. The runtime takes the form of a virtual machine executing portable code compliant with IEC 61131-3 standards. A formal model, comprising denotational semantics equations, has been devised to specify machine instruction decoding and operations, including arithmetic functions across various data types, arrays, and subprogram calls. The model also encompasses exception-handling mechanisms for runtime errors, such as division by zero and invalid array index access. This denotational model is translated into executable form using the functional F ♯ language. Verification involves comparing the actual implementation of the virtual machine against this executable model. Any disparities between the model and implementation indicate deviations from the specification. Implemented within the CPDev engineering environment, this approach ensures consistent and predictable control program execution across different target platforms.

From enterprise models to low-code applications: mapping DEMO to Mendix; illustrated in the social housing domain

Due to hyper-competition, technological advancements, regulatory changes, etc, the conditions under which enterprises need to thrive become increasingly turbulent. Consequently, enterprise agility increasingly determines an enterprise’s chances for success. As software development often is a limiting factor in achieving enterprise agility, enterprise agility and software adaptability become increasingly intertwined. As a consequence, decisions that regard flexibility should not be left to software developers alone. By taking a Model-driven Software Development (MDSD) approach, starting from DEMO ontological enterprise models and explicit (enterprise) implementation design decisions, the aim of this research is to bridge the gap from enterprise agility to software adaptability, in such a way that software development is no longer a limiting factor in achieving enterprise agility. Low-code technology is a growing market trend that builds on MDSD concepts and claims to offer a high degree of software adaptability. Therefore, as a first step to show the potential benefits to use DEMO ontological enterprise models as a base for MDSD, this research shows the design of a mapping from DEMO models to Mendix for the (automated) creation of a low-code application that also intrinsically accommodates run-time implementation design decisions.

Data-driven Energy-efficient Adaptive Sampling Using Deep Reinforcement Learning

This article presents a resource-efficient adaptive sampling methodology for classifying electrocardiogram (ECG) signals into different heart rhythms. We present our methodology in two folds: ( i ) the design of a novel real-time adaptive neural network architecture capable of classifying ECG signals with different sampling rates and ( ii ) a runtime implementation of sampling rate control using deep reinforcement learning (DRL). By using essential morphological details contained in the heartbeat waveform, the DRL agent can control the sampling rate and effectively reduce energy consumption at runtime. To evaluate our adaptive classifier, we use the MIT-BIH database and the recommendation of the AAMI to train the classifiers. The classifier is designed to recognize three major types of arrhythmias, which are supraventricular ectopic beats (SVEB), ventricular ectopic beats (VEB), and normal beats (N). The performance of the arrhythmia classification reaches an accuracy of 97.2% for SVEB and 97.6% for VEB beats. Moreover, the designed system is 7.3× more energy-efficient compared to the baseline architecture, where the adaptive sampling rate is not utilized. The proposed methodology can provide reliable and accurate real-time ECG signal analysis with performances comparable to state-of-the-art methods. Given its time-efficient, low-complexity, and low-memory-usage characteristics, the proposed methodology is also suitable for practical ECG applications, in our case for arrhythmia classification, using resource-constrained devices, especially wearable healthcare devices and implanted medical devices.

In-depth analysis on parallel processing patterns for high-performance Dataframes

The Data Science domain has expanded monumentally in both research and industry communities during the past decade, predominantly owing to the Big Data revolution. Artificial Intelligence (AI) and Machine Learning (ML) are bringing more complexities to data engineering applications, which are now integrated into data processing pipelines to process terabytes of data. Typically, a significant amount of time is spent on data preprocessing in these pipelines, and hence improving its efficiency directly impacts the overall pipeline performance. The community has recently embraced the concept of Dataframes as the de-facto data structure for data representation and manipulation. However, the most widely used serial Dataframes today (R, pandas) experience performance limitations while working on even moderately large data sets. We believe that there is plenty of room for improvement by taking a look at this problem from a high-performance computing point of view. In a prior publication, we presented a set of parallel processing patterns for distributed dataframe operators and the reference runtime implementation, Cylon [1]. In this paper, we are expanding on the initial concept by introducing a cost model for evaluating the said patterns. Furthermore, we evaluate the performance of Cylon on the ORNL Summit supercomputer.

A Study of the Effects and Benefits of Custom-Precision Mathematical Libraries for HPC Codes

Mathematical libraries are typically developed for use with the fixed-width data-paths on processors and target common floating-point formats such as IEEE binary32 and binary64 . To address the increasing energy consumption and throughput requirements of HPC, scientific computing and AI applications, libraries and hardware implementations now provide new floating-point formats, allowing mathematical function evaluations with different performance and accuracy trade-offs. In this article we present a methodology and its associated proof-of-concept tool to evaluate the benefits of custom accuracy of mathematical library calls in HPC and scientific computations. First, our tool collects for each call-site of a mathematical function the input- and output-data profile. Then, using a heuristic exploration algorithm, we estimate the minimal required accuracy by rounding the result to lower precisions. The data profile and accuracy measurement per call-site is used to speculatively select the mathematical function implementation with the most appropriate accuracy for a given scenario. We have tested the methodology with the Intel MKL Vector Math ( VM ) library, leveraging the predefined accuracy levels. We demonstrate the benefits of our approach on two real-world applications: SGP4 , a satellite tracking application, and PATMOS , a Monte Carlo neutron transport code. The robustness of the methodology is estimated by measuring the numerical accuracy of the resulting optimized code, against user-defined criteria. We experiment and discuss generalization across data-sets and finally propose a speculative runtime implementation for PATMOS . The experiment provides an insight into the performance improvements achievable by leveraging the control of per-function call-site accuracy-mode execution of the Intel compiler SVML library. We show benefits from 13 to 55 percent in time reduction for the PATMOS use case.

Concurrency Analysis in Dynamic Dataflow Graphs

Dynamic dataflow scheduling enables effective exploitation of concurrency while making parallel programming easier. To this end, analyzing the inherent degree of concurrency available in dataflow graphs is an important task, since it may aid compilers or programmers to assess the potential performance a program can achieve via parallel execution. However, traditional concurrency analysis techniques only work for DAGs (directed acyclic graphs), hence the need for new techniques that contemplate graphs with cycles. In this paper we present techniques to perform concurrency analysis on generic dynamic dataflow graphs, even in the presence of cycles. In a dataflow graph, nodes represent instructions and edges describe dependencies. The novelty of our approach is that we allow concurrency between different iterations of the loops. Consequently, a set of concurrent nodes may contain instructions from different loops that can be proven independent. In this work, we provide a set of theoretical tools for obtaining bounds and illustrate implementation of parallel dataflow runtime on a set of representative graphs for important classes of benchmarks to compare measured performance against derived bounds.

A Mashup-Based Framework for Business Process Compliance Checking

Business process compliance ensures that the processes of an organisation are designed and executed according to the rules that govern it. We faced the challenge of building a compliance management system for a process-aware organisation and identified several needs that, despite having been identified in the literature, were only partially satisfied by existing approaches. The variability in the types of rules generally restricts the existing support for compliance checking to specific types of rules, a concrete phase of the business process management lifecycle, or certain information systems (ISs) for data retrieval. Motivated by this, we designed a conceptual framework for compliance checking that relies on the use of mashups for rule specification and checking, with the following advantages: (i) an open-ended set of rules can be specified by designing and connecting mashup components; (ii) (parts of) the definitions of the rules can be reused as needed; and (iii) the mashup-based compliance checking system can be integrated with ISs of the organisation, enabling the verification of actual facts on actions performed during the execution of a process (e.g., the existence of a document in a location). Design-time and run-time implementations of the framework were conducted and tested in a real setting.

Software portability based on retargetable runtime environment

Subject of Research. The paper presents research of approaches to portable software development at the level of binary and source code. We study such factors affecting portability as compatibility of target platforms at the level of software and binary application interfaces, standardization of programming languages, software architecture, the functionality of software target platforms and software tools. Modern approaches for software portability based on virtual runtimes for Java and the .NET platform are considered. Method. A method is proposed for software portability based on two- stage compilation and an architecture description language application for translator configuration. The method gives the possibility to solve the software portability problem at the level of program execution environment. We also present a new approach to self-tuning runtime implementation with such configuration parameters as architecture-dependent metadata — descriptions of target platforms. To generate a binary image of the runtime environment for a target platform, its source code is not required. Image generation is performed based on metadata that is part of an existing image used as a builder utility. Main Results. Implementation requirements for the program execution environment and its architecture at the level of functional components are determined. The novel approach for the runtime implementation is proposed which ensures portability without recompilation from the source code of both user applications and the runtime environment. A script for the runtime environment application has been developed to generate its binary image aimed at a target platform. Practical Relevance. Binary portability of the program execution environment allows reducing labor costs for cross-platform applications.

STEEL-RT: combining single task–single executor model and expanded scheduling to ease heterogeneity exploitation

The ever-increasing complexity in terms of heterogeneity and available parallelism of modern architectures, together with the growing software ecosystem in terms of application libraries and runtime systems are posing a new challenge in terms of programmability on top of the already difficult task of extracting high parallel performance. With the goal of simplifying the programmability at the extreme, we first present the single task–single executor (STSE) model, in which the execution entry point consists solely on a single task assigned to an abstract execution context or executor, representing the whole system platform. As a second contribution, we introduce the expanded scheduling operations that endow executors with additional runtime task scheduling capabilities, and explain how executors can be composed to express and exploit different architectural features at run time under the framework of a single/multiple–task/executor taxonomy. As a result, we introduce STEEL, a novel programming model built on these concepts and STEEL-RT, a coupled high-performance runtime implementation for it. We illustrate the potential of STEEL by means of runtime experiments on a modern heterogeneous architecture, showing that complex and efficient heterogeneous executions are accessible from a STSE approach.

Model-driven cloud resource management with OCCIware

Abstract Cloud computing has emerged as the main paradigm for hosting and delivering computing resources as services over Internet. It provides a delivery model for computing resources at infrastructure, platform, and software levels. However, there is a plethora of cloud providers offering different resource management interfaces. Due to this diversity, the consumption, provisioning, management, and supervision of cloud resources are subjected to four key issues, i.e., heterogeneity, interoperability, integration, and portability. To cope with these issues, Open Cloud Computing Interface (OCCI) is proposed as a community-based and open recommendation standard for managing any kind of cloud resources. Currently, only runtime implementations exist for OCCI, and each one targets a specific cloud service model such as Infrastructure as a Service (IaaS), Platform as a Service (PaaS), or Software as a Service (SaaS). Thus, OCCI lacks an approach to model and execute different OCCI artifacts. Our approach provides a generic modeling framework coupled with a generic runtime implementation. In this article, we propose the OCCIware approach, which represents the first approach to design, validate, generate, implement, deploy, execute, and supervise everything as a service with OCCI. This approach provides OCCIware Studio , the first model-driven tool chain for OCCI. It is built around OCCIware Metamodel , which defines the static semantics for the OCCI standard in Ecore and OCL. In addition, it proposes OCCIware Runtime , the first generic OCCI runtime implementation targeting all the cloud service models (IaaS, PaaS, and SaaS). OCCIware provides a unique and unified framework to manage OCCI artifacts and, at the same time, it represents a factory to build cloud domain-specific modeling frameworks where each framework targets a specific cloud domain. OCCIware has been applied in various cloud domains and use-cases, which validate its applicability.

Control of a Robotic Wheel-Chair Prototype for People with Walking Disabilities

In this paper we present a system that could be used to help people with walking disabilities. A system consists of a prototype mobile robot platform equipped with a control board and a remote computer system, running with image processing algorithms, was used to develop a system for physically disabled human to move freely in an environment. We used a camera to get visual information by a human and then arrived information was fed to a computer system. Information was processed with a run time implementation. Control of prototype was inter linked based on user-end data that shows desired direction of movement. Experiments were performed in controlled environment. Limitations and possible future works would also be identified.

Task Transition Scheduling for Data-Adaptable Systems

Data-adaptable embedded systems operate on a variety of data streams, which requires a large degree of configurability and adaptability to support runtime changes in data stream inputs. Data-adaptable reconfigurable embedded systems, when decomposed into a series of tasks, enable a flexible runtime implementation in which a system can transition the execution of certain tasks between hardware and software while simultaneously continuing to process data during the transition. Efficient runtime scheduling of task transitions is needed to optimize system throughput and latency of the reconfiguration and transition periods. In this article, we provide an overview of a runtime framework enabling the efficient transition of tasks between software and hardware in response to changes in system inputs. We further present and analyze several runtime transition scheduling algorithms and highlight the latency and throughput tradeoffs for two data-adaptable systems. To evaluate the task transition selection algorithms, a case study was performed on an adaptable JPEG2000 implementation as well as three other synchronous dataflow systems characterized by transition latency and communication load.

The Unicorn Runtime: Efficient Distributed Shared Memory Programming for Hybrid CPU-GPU Clusters

Programming hybrid CPU-GPU clusters is hard. This paper addresses this difficulty and presents the design and runtime implementation of Unicorn —a parallel programming model for hybrid CPU-GPU clusters. In particular, this paper proves that efficient distributed shared memory style programing is possible and its simplicity can be retained across CPUs and GPUs in a cluster, minus the frustration of dealing with race conditions. Further, this can be done with a unified abstraction, avoiding much of the complication of dealing with hybrid architectures. This is achieved with the help of transactional semantics (on shared global address spaces), deferred bulk data synchronization, workload pipelining and various communication and computation scheduling optimizations. We describe the said abstraction, our computation and communication scheduling system and report its performance on a few benchmarks like Matrix Multiplication , LU Decomposition and 2D FFT . We find that parallelization of coarse-grained applications like matrix multiplication or 2D FFT using our system requires only about 30 lines of C code to set up the runtime. The rest of the application code is regular single CPU/GPU implementation. This indicates the ease of extending parallel code to a distributed environment. The execution is efficient as well. When multiplying two square matrices of size $65,536\times 65,536$ , Unicorn achieves a peak performance of 7.88 TFlop/s when run over a cluster of 14 nodes with each node equipped with two Tesla M2070 GPUs and two 6-core Intel Xeon 2.67 GHz CPUs, connected over a 32 Gbps Infiniband network. In this paper, we also demonstrate that the Unicorn programming model can be efficiently used to implement high level abstractions like MapReduce. We use such an extension to implement PageRank and report its performance. For a sample web of 500 million web pages, our implementation completes a page rank iteration in about 18 seconds (on average) on a 14-node cluster.

Design and Implementation of the PULSAR Programming System for Large Scale Computing

The objective of the PULSAR project was to design a programming model suitable for large scale machines with complex memory hierarchies, and to deliver a prototype implementation of a runtime system supporting that model. PULSAR tackled the challenge by proposing a programming model based on systolic processing and virtualization. The PULSAR programming model is quite simple, with point-to-point channels as the main communication abstraction. The runtime implementation is very lightweight and fully distributed, and provides multithreading, message-passing and multi-GPU offload capabilities. Performance evaluation shows good scalability up to one thousand nodes with one thousand GPU accelerators.

Fast iterative graph computation with block updates

Scaling iterative graph processing applications to large graphs is an important problem. Performance is critical, as data scientists need to execute graph programs many times with varying parameters. The need for a high-level, high-performance programming model has inspired much research on graph programming frameworks. In this paper, we show that the important class of computationally light graph applications - applications that perform little computation per vertex - has severe scalability problems across multiple cores as these applications hit an early "memory wall" that limits their speedup. We propose a novel block-oriented computation model, in which computation is iterated locally over blocks of highly connected nodes, significantly improving the amount of computation per cache miss. Following this model, we describe the design and implementation of a block-aware graph processing runtime that keeps the familiar vertex-centric programming paradigm while reaping the benefits of block-oriented execution. Our experiments show that block-oriented execution significantly improves the performance of our framework for several graph applications.

Portable mapping of openMP to multicore embedded systems using MCA APIs

Multicore embedded systems are being widely used in telecommunication systems, robotics, medical applications and more.While they offer a high-performance with low-power solution, programming in an efficient way is still a challenge. In order to exploit the capabilities that the hardware offers, software developers are expected to handle many of the low-level details of programming including utilizing DMA, ensuring cache coherency, and inserting synchronization primitives explicitly. The state-of-the-art involves solutions where the software toolchain is too vendor-specific thus tying the software to a particular hardware leaving no room-for portability. In this paper we present a runtime system to explore mapping a high-level programming model, OpenMP, on to multicore embedded systems. A key feature of our scheme is that unlike the existing approaches that largely rely on POSIX threads, our approach leverages the Multicore Association (MCA) APIs as an OpenMP translation layer. The MCA APIs is a set of low-level APIs handling resource management, inter-process communications and task scheduling for multicore embedded systems. By deploying the MCA APIs, our runtime is able to effectively capture the characteristics of multicore embedded systems compared with the POSIX threads. Furthermore, the MCA layer enables our runtime implementation to be portable across various architectures. Thus programmers only need to maintain a single OpenMP code base which is compatible by various compilers, while on the other hand, the code is portable across different possible types of platforms. We have evaluated our runtime system using several embedded benchmarks. The experiments demonstrate promising and competitive performance compared to the native approach for the platform.

Analysis of the Task Superscalar Architecture Hardware Design

In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing some dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation.

Optimised implementation of adaptive GPC for low-order systems with time delays

In adaptive situations the comparatively large run-time computational burden and implementation complexity of the generalised predictive control (GPC) algorithm can prove troublesome. Presented is an optimised design to implement a GPC adaption mechanism for low-order systems. By adopting a compact state-space model and symbolically solving the underlying Riccati equations, an exact solution with a trivial code implementation is obtained. The proposed approach significantly reduces the computational and memory burden of the standard method, and gives improved performance over approximate schemes whilst exhibiting comparable overheads.

Unpicking the knot

Flexible and efficient runtime design requires an understanding of the dependencies among the components internal to the runtime and those between the application and the runtime. These dependencies are frequently unclear. This problem exists in all runtime design, and is most vivid in a metacircular runtime --- one that is implemented in terms of itself. Metacircularity blurs boundaries between application and runtime implementation, making it harder to understand and make guarantees about overall system behavior, affecting isolation, security, and resource management, as well as reducing opportunities for optimization. Our goal is to shed new light on VM interdependencies, helping all VM designers understand these dependencies and thereby engineer better runtimes. We explore these issues in the context of a high-performance Java-in-Java virtual machine. Our approach is to identify and instrument transition points into and within the runtime, which allows us to establish a dynamic execution context. Our contributions are: 1) implementing and measuring a system that dynamically maintains execution context with very low overhead, 2) demonstrating that such a framework can be used to improve the software engineering of an existing runtime, and 3) analyzing the behavior and runtime characteristics of our runtime across a wide range of benchmarks. Our solution provides clarity about execution state and allowable transitions, making it easier to develop, debug, and understand managed runtimes.

Development of Laguerre Neural-Network-Based Intelligent Sensors for Wireless Sensor Networks

The node of a wireless sensor network (WSN), which contains a sensor module with one or more physical sensors, may be exposed to widely varying environmental conditions, e.g., temperature, pressure, humidity, etc. Most of the sensor response characteristics are nonlinear, and in addition to that, other environmental parameters influence the sensor output nonlinearly. Therefore, to obtain accurate information from the sensors, it is important to linearize the sensor response and compensate for the undesirable environmental influences. In this paper, we present an intelligent technique using a novel computationally efficient Laguerre neural network (LaNN) to compensate for the inherent sensor nonlinearity and the environmental influences. Using the example of a capacitive pressure sensor, we have shown through extensive computer simulations that the proposed LaNN-based sensor can provide highly linearized output, such that the maximum full-scale error remains within <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm$</tex> </formula> 1.0% over a wide temperature range from <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 50 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}\hbox{C}$</tex></formula> to 200 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{ \circ}\hbox{C}$</tex></formula> for three different types of nonlinear dependences. We have carried out its performance comparison with a multilayer-perceptron-based sensor model. We have also proposed a reduced-complexity run-time implementation scheme for the LaNN-based sensor model, which can save about 50% of the hardware and reduce the execution time by four times, thus making it suitable for the energy-constrained WSN applications.