Runtime Variations Research Articles

A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs

Sound techniques for mapping soft real-time applications to resources are indispensable for meeting the application deadlines and minimizing objectives such as energy consumption, particularly on heterogeneous MPSoC architectures. For applications with input-dependent workload variations, static mappings are not able to sufficiently cope with the run-time variation, which can lead to deadline misses or unnecessary energy consumption. As a remedy, hybrid application mapping (HAM) techniques combine a design-time optimization with run-time management that adapts the mappings dynamically to the changes of the arriving input. This paper focuses on scenario-based HAM techniques. Here, the application input space is systematically clustered such that data inside the same scenario exhibit similar characteristics concerning workload when being processed under the same operating points. This static clustering of the input space into data scenarios has proven to be a good abstraction layer for simplifying the design and employment of high-quality run-time managers. However, existing state-of-the-art scenario-based HAM approaches neglect or underutilize the synergistic interplay between mapping selection and the usage of dynamic voltage/frequency scaling (DVFS) when adapting to workload variation. By combining mapping and DVFS selection, variations in the input can be either compensated by a complete re-mapping of the application, evoking a potential high reconfiguration overhead or by just changing the DVFS settings of the resources, offering a low-overhead adaptation alternative and thus significantly reducing the necessary overhead compared to DVFS-agnostic HAM. Furthermore, DVFS enables a fine-grained adaptation of a mapped application to the input data variation, e.g., by slowing down tasks with no impact on the end-to-end latency for the current input using low-frequency DVFS settings. It is shown that this combined approach can save even more energy than a pure mapping adaptation scheme, especially in the presence of data scenarios. In particular, scenario-based design operates as a catalyst for eliciting the synergies between a combined DVFS and mapping optimization and the peculiarities inside a data scenario, i.e., exploiting the commonalities inside a data scenario by perfectly tailored DVFS settings and task mapping. In this scope, this paper proposes two supplementary scenario-based DVFS-aware HAM approaches that consistently outperform existing state-of-the-art mapping approaches in terms of the number of deadline misses and energy consumption as we demonstrate in an empirical study on the basis of four different applications and three different architectures. It is also shown that these benefits still apply to target architectures with increasing mapping migration overheads, thwarting frequent mapping reconfigurations.

Tidal barrage operation optimization using moment-based control


 As decarbonization of energy systems becomes an imperative and the deployment of intermittent renewables increases, the operation of electrical grids becomes challenging. In this sense, tidal barrage schemes can supply clean and predictable energy with more flexibility than the more traditional wind and solar plants. However, the high infrastructure costs associated with tidal barrage plants hinders its deployment. An optimal operation is key to maximize energy output and assure the project’s feasibility.
 Recently, Ringwood and Faedo [3] introduced a novel approach to tidal barrage control by applying wave energy control techniques, with promising results. The model consists on a two-way tidal barrage scheme, where an analogy is made between latching/declutching algorithms applied in WEC control and holding/sluicing from tidal barrage. The optimization was done using the moment-based framework developed in [1] and [2], which can formulate linear and non-linear problems in a concave quadratic environment, thus allowing the application of efficient numerical solution algorithms. This preliminary study has a number of simplifying assumptions, leaving a pathway to further examine the optimal control problem.
 This paper extends the results of the analysis from [3] by adding complexities to the model. Crucially, the basin is modeled such as the area is a polynomial function of the water level, instead of assuming constant surface area. This will affect the operational head of the optimal solution, as the volume of water at the top of the basin will be higher than at the bottom. Another added constraint will be the minimum head that the turbine requires to generate electricity. Furthermore, a cost function is introduced to penalize the energy consumption of the sluice gates, as shown in figures 1.a) and 1.b). This not only increases the accuracy of the model, but in many cases improves the convergence of the algorithm by adding a quadratic term. Figure 2 shows the value of the overall energy yield (as a fraction of the energy output without penalty) and simulation run time (as a fraction of the run time without penalty) with different penalty coefficients.
 1.a) Sluice gate area without considering cost function
 1.b) Sluice gate area with penalty factor of 3
 
 
 2. Energy and run time variations with penalty
 
 

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

The Ferroelectric Field-Effect Transistor (FeFET) is an emerging technology enabling novel data-centric architectures that go far beyond von Neumann principles. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as a novel structure that offers for the first time disturb-free read operation along with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 10× larger memory window (MW) compared to conventional FeFETs. However, all the before-mentioned variations are amplified in such a new structure. This work analyses the impact of temperature variation for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels, and compared to conventional FeFET. Through our cross-layer framework, we demonstrate the severe impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even Hyperdimensional Computing is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a cross-layer manner is indispensable.

Runtime Variation in Big Data Analytics

The dynamic nature of resource allocation and runtime conditions on Cloud can result in high variability in a job's runtime across multiple iterations, leading to a poor experience. Identifying the sources of such variation and being able to predict and adjust for them is crucial to cloud service providers to design reliable data processing pipelines, provision and allocate resources, adjust pricing services, meet SLOs and debug performance hazards. In this paper, we analyze the runtime variation of millions of production Scope jobs on Cosmos, an exabyte-scale internal analytics platform at Microsoft. We propose an innovative 2-step approach to predict job runtime distribution by characterizing typical distribution shapes combined with a classification model with an average accuracy of &gt;96%, using an innovative interpretable machine-learning algorithm out-performing traditional regression models and better capturing long tails. We examine factors such as job plan characteristics and inputs, resource allocation, physical cluster heterogeneity and utilization, and scheduling policies. To the best of our knowledge, this is the first study on predicting categories of runtime distributions for enterprise analytics workloads at scale. Furthermore, we examine how our methods can be used to analyze what-if scenarios, focusing on the impact of resource allocation, scheduling, and physical cluster provisioning decisions on a job's runtime consistency and predictability.

New Approaches of Side-Channel Attacks Based on Chip Testing Methods

The state-of-the-art test infrastructure security is based on the assumption of preventing access to the sensitive information and the (publicly) accessible outputs or test infrastructure subset are supposed to not leak any secret information. In addition, for achieving functional safety requirements, the on-chip test infrastructure is re-used in-field and cannot be completely disabled after manufacturing test phase. Therefore, the access to the scan chains or similar test access ports which can lead to sensitive information needs to be restricted or encrypted to guarantee the security of the test infrastructure. However, in this work we show that having access to (small delay) test results on insensitive (public) outputs can in fact reveal secret data. Using real hardware, we have performed template attacks using the results of delay testing on the output of cryptographic circuits and were able to retrieve the key with very few test inputs. This template attack requires only a few random patterns on the victim device, which could be different from the device used for template building. In addition, the attack is also resilient against runtime variation and noise, as well as inaccuracies and down-sampling of delay testing measurements.

Performance of Deep Learning Pickers in Routine Network Processing Applications

Abstract Picking arrival times of P and S phases is a fundamental and time-consuming task for the routine processing of seismic data acquired by permanent and temporary networks. A large number of automatic pickers have been developed, but to perform well they often require the tuning of multiple parameters to adapt them to each dataset. Despite the great advance in techniques, some problems remain, such as the difficulty to accurately pick S waves and earthquake recordings with a low signal-to-noise ratio. Recently, phase pickers based on deep learning (DL) have shown great potential for event identification and arrival-time picking. However, the general adoption of these methods for the routine processing of monitoring networks has been held back by factors such as the availability of well-documented software, computational resources, and a gap in knowledge of these methods. In this study, we evaluate recent available DL pickers for earthquake data, comparing the performance of several neural network architectures. We test the selected pickers using three datasets with different characteristics. We found that the analyzed DL pickers (generalized phase detection, PhaseNet, and EQTransformer) perform well in the three tested cases. They are very efficient at ignoring large-amplitude transient noise and at picking S waves, a task that is often difficult even for experienced analysts. Nevertheless, the performance of the analyzed DL pickers varies widely in terms of sensitivity and false discovery rate, with some pickers missing a significant percentage of true picks and others producing a large number of false positives. There are also variations in run time between DL pickers, with some of them requiring significant resources to process large datasets. In spite of these drawbacks, we show that DL pickers can be used efficiently to process large seismic datasets and obtain results comparable or better than current standard procedures.

Robust and accurate regression-based techniques for period inference in real-time systems

With the growth in complexity of real-time embedded systems, there is an increasing need for tools and techniques to understand and compare the observed runtime behavior of a system with the expected one. Since many real-time applications require periodic interactions with the environment, one of the fundamental problems in guaranteeing their temporal correctness is to be able to infer the periodicity of certain events in the system. The practicability of a period inference tool, however, depends on both its accuracy and robustness (also its resilience) against noise in the output trace of the system, e.g., when the system trace is impacted by the presence of aperiodic tasks, release jitters, and runtime variations in the execution time of the tasks. This work (i) presents the first period inference framework that uses regression-based machine-learning (RBML) methods, and (ii) thoroughly investigates the accuracy and robustness of different families of RBML methods in the presence of uncertainties in the system parameters. We show, on both synthetically generated traces and traces from actual systems, that our solutions can reduce the error of period estimation by two to three orders of magnitudes w.r.t. the state of the art.

Brain-Inspired Computing for Circuit Reliability Characterization

Transistor scaling steadily approaches fundamental limits. Sustaining circuit reliability becomes an overwhelming challenge for foundries. Therefore, early and rapid characterization of degradation effects impacting the circuits transistors becomes essential. Such degradation effects are caused by design-time variation due to manufacturing variability and/or run-time variation due to transistor aging. In this work, we are the first to employ Brain-Inspired Hyperdimensional computing (HDC) for circuit reliability. HDC is an emerging light-weight machine-learning solution. Nowadays, it is mainly applied to bio-signal processing. We bring the research of HDC to the next level by demonstrating how it can be applied to address the challenges in circuit reliability. This has far-reaching consequences due to the large savings achieved by 1) reducing the amount of training data, 2) removing the need to send the data to the Cloud for model training, and 3) significantly speeding up the characterization and classification tasks. We demonstrate the viability of HDC, using SRAM and other circuits as an example. HDC outperforms traditional machine learning methods, such as support vector machine, in accuracy and requires up to 20x fewer training samples. Our implementation and analysis are based on industrial 14 nm FinFET fully calibrated with Intel measurements.

Securing IoT Devices Using Dynamic Power Management: Machine Learning Approach

The shift in paradigm from cloud computing toward edge has resulted in faster response times, a more secure and energy-efficient edge. Internet-of-Things (IoT) devices form a vital part of the edge, but despite legions of benefits it offers, increasing vulnerabilities and escalation in malware generation has rendered them insecure. Software-based approaches are prominent in malware detection, but they fail to meet the requirements for IoT devices. Dynamic power management (DPM) is architecture agnostic and inherently pervasive component existing in all low-power IoT devices. In this article, we demonstrate dynamic voltage and frequency scaling (DVFS) states form a signature pertinent to an application, and its runtime variations comprise of features essential for securing IoT devices against malware attacks. We have demonstrated this proof of concept by performing experimental analysis on a Snapdragon 820 mobile processor, hosting the Android operating system (OS). We developed a supervised machine learning model for application classification and malware identification by extracting features from the DVFS states time series. The experimental results show $> 0.7~F1$ score in classifying different android benchmarks and >0.88 in classifying benign and malware applications when evaluated across different DVFS governors. We also performed power measurements under different governors to evaluate power-security aware governor. We have observed higher detection accuracy and lower power dissipation under settings of the ondemand governor.

Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems

Domain-specific systems-on-chip, a class of heterogeneous many-core systems, are recognized as a key approach to narrow down the performance and energy-efficiency gap between custom hardware accelerators and programmable processors. Reaching the full potential of these architectures depends critically on optimally scheduling the applications to available resources at runtime. Existing optimization-based techniques cannot achieve this objective at runtime due to the combinatorial nature of the task scheduling problem. As the main theoretical contribution, this paper poses scheduling as a classification problem and proposes a hierarchical imitation learning (IL)-based scheduler that learns from an Oracle to maximize the performance of multiple domain-specific applications. Extensive evaluations with six streaming applications from wireless communications and radar domains show that the proposed IL-based scheduler approximates an offline Oracle policy with more than 99% accuracy for performance- and energy-based optimization objectives. Furthermore, it achieves almost identical performance to the Oracle with a low runtime overhead and successfully adapts to new applications, many-core system configurations, and runtime variations in application characteristics.

Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation

Scaling supply voltage to the near-threshold voltage (NTV) region is an effective approach for energy-constrained circuit design at the cost of acceptable performance reduction. However, by operating in the NTV region, the sensitivity of circuits to process and runtime variations significantly aggravates. Therefore, the performance and power consumption of a circuit is largely impacted by the variabilities, which affects the operating voltage for the most efficient computation, i.e., the minimum energy point (MEP). Accordingly, finding an optimum operating voltage for near-threshold computing (NTC) to account for variabilities is very challenging. In this article, we propose an MEP calibration and adaptation approach based on machine learning to tune for minimal energy operation on a per-chip basis by considering process and runtime variations. In the proposed approach, the optimal supply voltage of each chip is determined during manufacturing tests by characterizing dynamic and leakage power and at runtime by considering the impact of temperature variation. The presented method does not require costly power measurement circuitry on chip. The simulation results show that the proposed method has high MEP prediction accuracy and achieves near-optimal operation by only 1.2% higher energy consumption compared with the optimal operation.

Bayesian Optimized Mixture Importance Sampling for High-Sigma Failure Rate Estimation

In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason, a thorough memory failure rate assessment is imperative for correct circuit operation and yield improvement. In this regard, Monte Carlo (MC) simulations have been used as the conventional method to estimate the variability induced failure rate of memory components. However, MC methods become infeasible when estimating rare events such as high-sigma failure rates. To this end, importance sampling (IS) methods have been proposed which reduce the number of required simulations substantially. However, existing methods still suffer from inaccuracies and high computational efforts, in particular for high-sigma problems. In this article, we fill this gap by presenting an efficient mixture IS approach based on Bayesian optimization, which deploys a surface model of the objective function to find the most probable failure points. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and the higher trustworthiness of the estimated failure rate by accurately exploring the design space. The approach is evaluated on a 6T-SRAM cell as well as a master–slave latch based on a 28-nm FDSOI process. The results show an improvement in accuracy, resulting in up to $63\times $ better accuracy in estimating failure rates compared to the best state-of-the-art solutions on a 28-nm technology node.

Enhancing the Accuracy and Robustness of a Compressive Sensing Based Device-Free Localization by Exploiting Channel Diversity.

As an emerging and promising technique, device-free localization (DFL) estimates target positions by analyzing their shadowing effects. Most existing compressive sensing (CS)-based DFL methods use the changes of received signal strength (RSS) to approximate the shadowing effects. However, in changing environments, RSS readings are vulnerable to environmental dynamics. The deviation between runtime RSS variations and the data in a fixed dictionary can significantly deteriorate the performance of DFL. In this paper, we introduce ComDec, a novel CS-based DFL method using channel state information (CSI) to enhance localization accuracy and robustness. To exploit the channel diversity of CSI measurements, the DFL problem is formulated as a joint sparse recovery problem that recovers multiple sparse vectors with common support. To solve this problem, we develop a joint sparse recovery algorithm under the variational Bayesian inference framework. In this algorithm, dictionaries are parameterized based on the saddle surface model. To adapt to the environmental changes and different channel characteristics, dictionary parameters are modelled as tunable parameters. Simulation results verified the superior performance of ComDec as compared with other state-of-the-art CS-based DFL methods.

EdgeFlow: Open-Source Multi-layer Data Flow Processing in Edge Computing for 5G and Beyond

Edge computing has evolved to be a promising avenue to enhance system computing capability by offloading processing tasks from the cloud to edge devices. In this article, we propose a multi-layer edge computing framework called EdgeFlow. In this framework, different nodes ranging from edge devices to cloud data centers are categorized into corresponding layers and cooperate for data processing. EdgeFlow can deal with the trade-off between the computing and communication capabilities so that the tasks can be assigned to each layer optimally. At the same time, resources are carefully allocated throughout the whole network to mitigate performance fluctuation. The proposed open-source data flow processing framework is implemented on a platform that can emulate various computing nodes in multiple layers and corresponding network connections. Evaluated on the face recognition scenario, EdgeFlow can significantly reduce task finish time and perform more tolerance to run-time variations, compared with pure cloud computing, pure edge computing, and Cloudlet. Potential applications of EdgeFlow, including network function virtualization, Internet of Things, and vehicular networks, are also discussed at the end of this article.

PACoGen: A Hardware Posit Arithmetic Core Generator

This paper proposes open-source hardware Posit Arithmetic Core Generator (PACoGen) for the recently developed universal number posit number system, along with a set of pipelined architectures. The posit number system composed of a run-time varying exponent component, which is defined by a composition of varying length “regime-bit” and “exponent-bit” (with a maximum size of ES bits, the exponent size). This in effect also makes the fraction part to vary at run-time in size and position. These run-time variations inherit an interesting hardware design challenge for posit arithmetic architectures. The posit number system, being at an infant stage of its development, possess very limited hardware solutions for its arithmetic architectures. In this view, this paper targets the algorithmic development and generic HDL generators (PACoGen) for basic posit arithmetic. The proposed open source PACoGen currently includes the adder/subtractor, multiplier, and division arithmetic. The PACoGen can provide the Verilog HDL code respective posit arithmetic for any given posit word width (N) and exponent size (ES), as defined under the posit number system. Further, pipelined architectures of 32-bit posit with 6-bit exponent size are also proposed and discussed for addition/subtraction, multiplication, and division arithmetic. The proposed posit arithmetic architectures are demonstrated on the Virtex-7 (xc7vx330t-3ffg1157) FPGA device as well as Nangate 15 nm ASIC platform. The PACoGen would open a gateway for further posit arithmetic hardware exploration and evaluation.

On-line Damping Estimation in Road Vehicle Semi-active Suspension Systems

Abstract Semi-active suspensions are characterized by a run-time variation of the damping force according to the actual vehicle dynamics. Depending on the specific technology, the damping ratio is selected by indirectly acting on a related variable, e.g., in magneto-rheological devices, the viscosity of the damper fluid is changed under the action of a magnetic field generated by a manipulated current. Unexpected changes of the device, e.g., due to aging or damages, may affect the performance of the suspension, as the current is no longer mapped onto the nominal damping ratio. In this paper, an on-line damping estimation method is proposed for anomaly detection in semi-active dampers, based on inertial measurements only. Experimental tests on a vehicle set-up show the effectiveness of the proposed approach.

Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design

Cryptographic cores are known to leak information about their private key due to runtime variations, and there are many well-known attacks that can exploit this timing channel. In this paper, we study how information theoretic measures can quantify the amount of key leakage that can be exacted from runtime measurements. We develop and analyze 22 Rivest–Shamir–Adleman (RSA) hardware designs—each with unique performance optimizations, timing channel mitigation techniques, or discretization/randomization countermeasures. We demonstrate the effectiveness of information theoretic measures for quantifying timing leakage through correlation analysis of information theoretic measurements and attack results. Experimental results show that mutual information is a promising technique for quantifying timing leakage for RSA, advanced encryption standard, and elliptic curve cryptography ciphers, i.e., the mutual information correlates to being able to successfully guess the value of the private key. This is an important step toward a hardware security metric which allows designers to reason about security alongside traditional hardware design metrics like area, performance, and power.

Dynamic Evolutionary Multiobjective Optimization for Raw Ore Allocation in Mineral Processing

Raw ore allocation in mineral processing is crucial for improving the utilization ratio of nonrenewable raw mineral resources. Allocation of raw ore is a nonlinear, multiobjective programming problem. Such a problem is usually modeled under the assumption that the production process is stationary and the model parameters are deterministic. However, in practice, variations in equipment capability and runtime lead to frequent changes of the model parameters including the constraints. To address the above-mentioned issues, this paper formulates a raw ore allocation in mineral processing as a dynamic multiobjective optimization problem. To solve this problem, a new variant of the elitist nondominated sorting genetic algorithm (D-NSGA-II) is proposed, which employs NSGA-II as the basic component assisted by random immigrant scheme, a gradient-based local search strategy, and a mechanism for detecting environmental changes. Simulations are carried out and the results show that the proposed algorithm can efficiently achieve the Pareto front of the multiobjective raw ore allocation dynamic optimization problem. It can simultaneously converge fast while maintaining good population diversity, in particular, in the presence of large environmental changes.

Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing

Power and energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultralow power and energy-harvested systems. Aggressive voltage scaling and in particular near-threshold computing is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runtime variation. Temperature variation is one of the major sources of performance variation. In this paper, we study the impact of temperature variation on the circuit behavior in the near-threshold voltage region and show that the ambient temperature has a huge impact on the metrics such as circuit delay, power, and energy consumption. We also propose a low-cost, ambient temperature-aware voltage scaling technique to reduce the unnecessary energy overhead caused by temperature variation. Simulation results show that our proposed approach reduces the energy consumption by more than 1.95×.

Performance-Monitoring-Based Traffic-Aware Virtual Machine Deployment on NUMA Systems

Virtualization technology enables multiple virtual machines (VMs) to share a single physical server. Commercial servers increasingly use the nonuniform memory access (NUMA) architecture due to its scalable memory performance. However, multiple VMs running on a NUMA physical server will cause performance overheads such as remote memory access latency and shared microarchitectural resource contention, which makes the VM performance less efficient and stable. These performance overheads are mainly caused by memory traffic from data-intensive workloads. In this paper, we propose a traffic-aware VM optimization (TAVO) scheme on NUMA systems. Based on the performance monitoring of the data traffic and CPU/memory resource usages in the system, TAVO addresses VM memory access locality and shared resource contention problems via automatic VM initial placement and NUMA-aware VM online scheduling. Our experimental results show that TAVO improves VM performance in terms of benchmark runtime by up to 22.6% compared with the default KVM CFS scheduler. TAVO also achieves a much stable performance with benchmark's average runtime variation under 3%.