Runtime Reconfigurable Architecture Research Articles

Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate

In this study, we introduce the area efficient low complex runtime reconfigurable architecture design methodology based on Skyrmion logic for universal logic gate (ULG) i.e. NOR/NAND implementation using micromagnetic simulations. We have modelled the two input 3D device structure using bilayer ferromagnet/heavy metal where the magnetic tunnel junctions inject and detect the input and output skyrmions by exploiting the input reversal mechanism. The implementation of NOR and NAND is performed using this same device where it is reconfigured runtime with enhanced tunability by the ON and OFF state of current passing through a non magnetic metallic gate respectively. This gate acts as a barrier for skyrmion motion (additional control mechanism) to realize the required Skyrmion logic output states. To the best of authors’s knowledge the boolean optimizations and the mapping logic have been presented for the first time to demonstrate the functionalities of the NOR/NAND implementation. This proposed architecture design methodology of ULG leads to reduced device footprint with regard to the number of thin film structures proposed, low complexity in terms of fabrication and also providing runtime reconfigurability to reduce the number of physical designs to achieve all truth table entries (∼75% device footprint reduction). The proposed 3D ULG architecture design benefits from the miniaturization resulting in opening up a new perspective for magneto-logic devices.

AM&FT: An Aging Mitigation and Fault Tolerance Framework for SRAM-Based FPGA in Space Applications

Field programmable gate arrays (FPGAs) have become very widely used devices in space applications, and their runtime reconfigurable architecture allows for the area and power acceleration for complex applications. However, FPGAs are increasingly susceptible to aging effects and failures due to harsh space environments and long operation cycles, which reduce the reliability and lifetime of such devices. Although offline aging-aware layout-based methods are effective in aging mitigation, existing studies ignore the fault tolerance needs of the task and the layout strategy will completely fail after a hard failure occurs. This paper presents a reliability framework AM&FT for SRAM-based FPGAs in space applications to support on-chip aging mitigation and fault tolerance. We use an Integer Linear Programming (ILP) model to solve mapping relationships between tasks and reconfigurable blocks (Rbs) in the offline phase to achieve the aging and reliability-aware layout strategy. Second, the ILP model is incorporated into the Design Space Exploration (DSE) to generate a set of layout strategies to tolerate hard faults. Moreover, the state model is used for runtime fault management to handle the impact of different types of faults on the device. Experimental results demonstrate that our framework achieves FPGA on-chip aging mitigation and fault tolerance. Compared with the existing methods, AM&FT can guarantee the fault tolerance requirements of tasks and give priority to guarantee the Quality of Service (QoS) of critical tasks under the condition of hard faults accumulation. In addition, our framework delivers up to [Formula: see text] mean time to failure (MTTF) than the baseline.

AMROFloor: An Efficient Aging Mitigation and Resource Optimization Floorplanner for Virtual Coarse-Grained Runtime Reconfigurable FPGAs

With the rapid reduction of CMOS process size, the FPGAs with high-silicon accumulation technology are becoming more sensitive to aging effects. This reduces the reliability and service life of the device. The offline aging-aware layout planning based on balance stress is an effective solution. However, the existing methods need to take a long time to solve the floorplanner, and the corresponding layout solutions occupy many on-chip resources. To this end, we proposed an efficient Aging Mitigation and Resource Optimization Floorplanner (AMROFloor) for FPGAs. First, the layout solution is implemented on the Virtual Coarse-Grained Runtime Reconfigurable Architecture, which contributes to avoiding rule constraints for placement and routing. Second, the Maximize Reconfigurable Regions Algorithm (MRRA) is proposed to quickly determine the RRs’ number and size to save the solving time and ensure an effective solution. Furthermore, the Resource Combination Algorithm (RCA) is proposed to optimize the on-chip resources, reducing the on-Chip Resource Utilization (CRU) while achieving the same aging relief effect. Experiments were simulated and implemented on Xilinx FPGA. The results demonstrate that the AMROFloor method designed in this paper can extend the Mean Time to Failure (MTTF) by 13.8% and optimize the resource overhead by 19.2% on average compared to the existing aging-aware layout solutions.

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures

Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) allow areaand power-efficient acceleration of complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability and lifetime of such systems. Aging mitigation and fault tolerance techniques for the reconfigurable fabric become essential to realize dependable reconfigurable architectures. This article presents an accelerator diversification method that creates multiple configurations for runtime reconfigurable accelerators that are diversified in their usage of Configurable Logic Blocks (CLBs). In particular, it creates a minimal number of configurations such that all single-CLB and some multi-CLB faults can be tolerated. For each fault we ensure that there is at least one configuration that does not use that CLB. Second, a novel runtime accelerator placement algorithm is presented that exploits the diversity in resource usage of these configurations to balance the stress imposed by executions of the accelerators on the reconfigurable fabric. By tracking the stress due to accelerator usage at runtime, the stress is balanced both within a reconfigurable region as well as over all reconfigurable regions of the system. The accelerator placement algorithm also considers faulty CLBs in the regions and selects the appropriate configuration such that the system maintains a high performance in presence of multiple permanent faults. Experimental results demonstrate that our methods deliver up to 3.7× higher performance in presence of faults at marginal runtime costs and 1.6× higher MTTF than state-ofthe-art aging mitigation methods.

Leveraging FPGAs for Accelerating Short Read Alignment.

One of the key challenges facing genomics today is how to efficiently analyze the massive amounts of data produced by next-generation sequencing platforms. With general-purpose computing systems struggling to address this challenge, specialized processors such as the Field-Programmable Gate Array (FPGA) are receiving growing interest. The means by which to leverage this technology for accelerating genomic data analysis is however largely unexplored. In this paper, we present a runtime reconfigurable architecture for accelerating short read alignment using FPGAs. This architecture exploits the reconfigurability of FPGAs to allow the development of fast yet flexible alignment designs. We apply this architecture to develop an alignment design which supports exact and approximate alignment with up to two mismatches. Our design is based on the FM-index, with optimizations to improve the alignment performance. In particular, the n-step FM-index, index oversampling, a seed-and-compare stage, and bi-directional backtracking are included. Our design is implemented and evaluated on a 1U Maxeler MPC-X2000 dataflow node with eight Altera Stratix-V FPGAs. Measurements show that our design is 28 times faster than Bowtie2 running with 16 threads on dual Intel Xeon E5-2640 CPUs, and nine times faster than Soap3-dp running on an NVIDIA Tesla C2070 GPU.

Bit plane matching based variable block size motion estimation method and its hardware architecture

Variable Block Size Motion Estimation (VBSME) is one of the most important features of state-of-theart video encoders. In the H.264/AVC encoder, the computational complexity of integer motion estimation is about 75%. Therefore, reducing this complexity is one of the key points to provide low power video encoding. In this paper, a reconfigurable bit plane matching based VBSME method and a runtime reconfigurable hardware architecture are proposed to allow low-power consumer electronic devices to make a trade-off between power requirements and motion estimation (ME) accuracy. The proposed ME method is the only low complexity ME algorithm proposed in the literature so far that can provide compatible ME accuracy for lower block sizes compared to the sum of absolute difference (SAD) criterion. A new data path for the computation of the matching criterion in the proposed hardware architecture which has a fully arithmetic structure is proposed to improve the previously utilized LUT based architectures by having a fully arithmetic structure.

A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

Runtime reconfigurable system‐on‐chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex‐4 FPGAs. The system architecture will also be presented to provide a realistic application example.

Low power reconfigurable sub-band filter bank ASIC for MP3 decoder

There is an ever demanding need to develop low power audio devices using MP3 technology. From the profiled results of MP3 algorithm on ARM processors, it has been observed that the synthesis filter bank in the audio decoder consumes maximum power. Hence, to reduce the power consumption of the filter bank, we developed an IEEE 754 single precision floating-point runtime reconfigurable architecture. The proposed architecture consumes less power at run time as the last 12 bits of the mantissa part of the synthesis filter coefficients are zero most of the time and, hence, the corresponding multipliers will be switched off. Since the active multipliers during inverse polyphase quadrature mirror filter banks (IPQMF) are less, we are able to achieve low powered decoding process without significantly compromising on the accuracy and speed. We synthesised and simulated the architecture using 0.35 μm process technology under synopsys environment. A uniform worst case power reduction of 23.7% has been achieved in the frequency range from 1 MHz to 20 MHz when all the multipliers are in active state.

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC

Data-intensive processing in embedded systems is receiving much attention in multimedia computing and high-speed telecommunications. The memory bandwidth problem of traditional von Neumann architectures, however, is impairing processor efficiency. On the other hand, ASIC designs suffer from skyrocketing manufacturing costs and long development cycles. This results in an increasing need for postfabrication programmability at both software and hardware levels. FPGAs provide maximum flexibility with their fine-grained architecture but bring severe overhead in timing, area, and power consumption. Wordor subword-oriented runtime reconfigurable architectures offer highly parallel, scalable solutions combining hardware performance with software flexibility.1 Their coarser granularity reduces area, delay, power consumption, and reconfiguration time, but they introduce trade-offs in processing-element design.

On Enforced Convergence of ACO and its Implementation on the Reconfigurable Mesh Architecture Using Size Reduction Tasks

In this paper we show that size reduction tasks can be used for executing iterative randomized metaheuristics on runtime reconfigurable architectures so that an improved throughput and better solution qualities are obtained compared to conventional architectures that do not allow runtime reconfiguration. In particular, the problem of executing ant colony optimization (ACO) algorithms on a dynamically reconfigurable mesh architecture is studied. It is shown how ACO can be implemented such that the convergence behavior of the algorithm can be used to dynamically reduce the size of the submesh that is needed for execution. Furthermore we propose a method to enforce the convergence of ACO leading to a faster reduction process. This increases the throughput of ACO algorithms on runtime reconfigurable meshes. The increased throughput is used for repeated runs of ACO algorithms on a given set of problem instances which significantly improves the obtained solution quality.

HW/SW codesign techniques for dynamically reconfigurable architectures

Hardware/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digital-systems design. However, no previous work has been carried out in order to define a HW/SW codesign methodology with dynamic scheduling for run-time reconfigurable architectures. In addition, all previous approaches to reconfigurable computing multicontext scheduling are based on static-scheduling techniques. In this paper, we present three main contributions: 1) a novel HW/SW codesign methodology with dynamic scheduling for discrete event systems using dynamically reconfigurable architectures; 2) a new dynamic approach to reconfigurable computing multicontext scheduling; and 3) a HW/SW partitioning algorithm for dynamically reconfigurable architectures. We have developed a whole codesign framework, where we have applied our methodology and algorithms to the case study of software acceleration. An exhaustive study has been carried out, and the obtained results demonstrate the benefits of our approach.