RTL Coding Research Articles

47‐3: Novel Visually Lossless Display Interface Technique using Adaptive Sub‐color Optimization and DCT (Discrete Cosine Transform)

A novel bandwidth‐reduced display interface technique using adaptive sub‐color optimization with DCT (AS‐DCT) has been proposed to be able to lower both implementation cost and power consumption with visually lossless image quality for high resolution display products. A DCT conversion is applied to 1‐D line pixel data, and 50% of the redundant data has been compressed adaptively based on both sub‐color priority and the distribution of AC data components. A PSNR of about 45.86dB level was achieved for a given set of test images, and it was implemented using RTL coding in a FPGA to verify image quality and logic size level on an actual display system. Through the proposed technique, it is expected that it can easily reduce display data bandwidth without latency and lower its implementation cost for future display devices, such as 8K/16K resolutions, 240Hz/480Hz refresh rates, immersive AR/VR, Light field displays and beyond.

Assessment of Winograd-based processor element for CNN processor and ASIC implementation of convolution processor element

The convolutional neural network (CNN) is the most widely used machine learning technique within the fields of image and video processing. It is primarily used to categorize images using vast datasets. This require a lot of calculations. The effectiveness of a field-programmable gate array (FPGA) as a hardware accelerator for CNNs will give excellent performance at low power budgets. The employment of the Winograd algorithm can reduce the number of processing stages in CNN. 2-D convolution is employed for the bulk of calculations in CNNs. The tactic for computing convolution for smaller filter sizes that uses Winograd minimum filtering is the handiest. The comparison of computation complexity for multiplications will be performed using Matlab. The architecture of the Winograd-based processing element, RTL coding in Verilog HDL, and the test bench are designed to examine the performance. The Xilinx Vivado / Cadence tool will be used to implement the processing element in the convolution unit on an FPGA or ASIC.

Adaptive Counter Clock Gated S-Box Transformation Based AES Algorithm of Low Power Consumption and Dissipation in VLSI System Design

Advanced Encryption Standard (AES) is an effective algorithm trending today. According to the key length, it works efficiently. Here three types of key lengths are used such as 128, 192, and 256 bits. This paper introduced an Adaptive Counter-Clock (ACC) S-Box algorithm. This algorithm rectifies the error during data encryption and secure data from hackers. In this paper, we have done power consumption, power dissipation, and reduced the area size. Field Programmable Gate Array (FPGA) is utilized for hardware execution in the encryption process. Inverse Mix Column, Inverse Sub Bytes (S-Box) and Inverse Shift Row stages takes place in the decryption, so that the receiver can read the message in plain text which was sent by the sender. For this the receiver should have the same key used by the sender for encryption process. RTL coding is done using Verilog HDL, Xilinx ISE 14.7 FPGA will be used in the implementation.

Core i7 Specific Energy Efficient Ram Design for IoT Application

Fundamental memory has turned out to be one of largest contributors to overall energy consumption and offer many opportunities for power reduction. Power dissipation plays important role in portable products that can store, receive and transmit data because in each operation cycle the power is consumed by the operator. The goal of this paper is to use Frequency scaling approach in Random Access Memory to minimize power dissipation by the help of High Speed Transceiver Logic (HSTL) input output standard. These techniques cover RTL coding. This research suggest that there is 75% reduction clock power 66.66% reduction in Signal power, (35.20% to 47.77%) reduction in IOs power when the frequency are minimize. This design is implemented on Artex-7.

Simulink Model Based Design and FPGA Implementation of Multi-Channel DTV Transmitter

This paper presents DTV transmitter design based on the SW/HW hybrid architecture. Parts of the DTV transmission algorithm with less computational complexity are processed by the SW module in PC whereas computationally intensive parts are processed by the HW module in FPGA. The two parts are interconnected by the high speed serial link. To provide the multi-channel DTV signal, we design an architecture where several DTV waveforms are generated simultaneously and combined in the digital domain. We propose a simulink based communication system design and verification methodology. This method reduces the design and verification time of the prototype system significantly and reduces the RTL coding and verification burden.

Implementation of Channel Estimation and Modulation Technique for MIMO System

Future wireless communication system have to be designed to integrate features such as high data rates, high quality of service and multimedia in the existing communication framework. Increased demand in wireless communication system has led to demand for higher network capacity and performance. Higher bandwidth, optimized modulation offer practically limited potential to increase the spectral efficiency. Hence MIMO systems utilizes space multiplex by using array of antenna’s for enhancing the efficiency at particular utilized bandwidth. MIMO use multiple inputs multiple outputs from single channel. These systems defined by spectral diversity and spatial multiplexing. The aim of this paper is to design and implement of channel estimation method and modulation technique for MIMO system. The design specifications are obtained using MATLAB. The RTL coding is carried for the design to be implemented on Xilinx FPGA.