Rowhammer Research Articles

Mission-Critical Systems, Paradox of Hamming Code, Row Hammer Effect, ‘Trojan Horse’ of the Binary System and Numeral Systems with Irrational Bases

Mission-Critical Systems, Paradox of Hamming Code, Row Hammer Effect, ‘Trojan Horse’ of the Binary System and Numeral Systems with Irrational Bases

A row hammer pattern analysis of DDR2 SDRAM

A DDR2 SDRAM test setup implemented on the Griffin III ATE test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests. The analysis confirms that the row hammer effect is caused by a charge excitation process depending on the number of stress activation cycles. The stress has to occur in the local neighborhood of the cells under test. Shallow impurity levels support the responsible charge carrier transport process in the used DDR2 SDRAM technology.

Counter-Based Tree Structure for Row Hammering Mitigation in DRAM

Scaling down DRAM technology degrades cell reliability due to increased coupling between adjacent DRAM cells, commonly referred to as crosstalk. Moreover, high access frequency of certain cells (hot cells) may cause data loss in neighboring cells in adjacent rows due to crosstalk, which is known as row hammering . In this work, the goal is to mitigate row hammering in DRAM cells through a Counter-Based Tree (CBT) approach. This approach uses a tree of counters to detect hot rows and then refreshes neighboring cells. In contrast to existing deterministic solutions, CBT utilizes fewer counters that makes it practically feasible to be implemented on-chip. Compared to existing probabilistic approaches, CBT more precisely refreshes rows vulnerable to row hammering based on their access frequency. Experimental results on workloads from three benchmark suites show that CBT can reduce the refresh energy by more than 60 percent and nearly 70 percent in comparison to leading probabilistic and deterministic approaches, respectively. Furthermore, hardware evaluation shows that CBT can be easily implemented on-chip with only a nominal overhead.

Suppression of Row Hammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology

The row hammer effect has become a reliability issue that cannot be ignored in sub-30-nm dynamic random-access memory (DRAM) products because of the narrow isolation spacing between the array devices. Improving the row hammer effect via fabrication process optimization is first proposed in this paper. An additional phosphorus (P) implantation with energy and dosage modification applied in the common source area between two adjacent buried word lines of the access devices and energy adjustment of the well implantation are applied to provide a doping profile modification in the array device. With the proper implantation setting of the high energy and 2X dosage in the additional P implantation, a localized shielding effect from the electric field by a depletion effect could be used to reduce the chances of hammering gate-induced electrons in the channel leaking to the adjacent access device. This proposed mechanism could be supported by the experimental results of the doping profile. Therefore, the row hammer effect can be suppressed by up to 30% in normalized fail bit counts. This proposed methodology could be used in future generations to suppress the row hammer effect in DRAMs.

Statistical distributions of row-hammering induced failures in DDR3 components

As process technology shrinks down, the distances among storage cells in DRAMs gets smaller. Smaller distances among cells cause the cell-to-cell interference to increase. Due to the proximity to neighboring cells, a DRAM cell loses the stored charge in the cell faster with repetitive accesses on an adjacent row. Such phenomenon is known as row hammering failure and has been reported to occur in the commodity DDR3 components manufactured with the process technologies under 3× nm technology.This work developed a statistical model of row hammering failures based on experimental results obtained with commodity DDR3 SDRAMs of 3× nm technology. The statistical distribution for the failing rows with respect to the number of hammerings matched the normal distribution. The means μHMR and standard deviations σHMR of the number of hammerings that cause row hammering failure were apparently different among three different manufacturers. The means of the manufacturers varied by more than 200% and could be sufficiently used to characterize the reliability of the device from a row hammering stress perspective. Based on the derived statistical model, the failed parts-per-million (ppm) was calculated to give, on average, 164.6, 82.6 and 22.2, respectively, for the manufacturers.

Architectural Support for Mitigating Row Hammering in DRAM Memories

DRAM scaling has been the prime driver of increasing capacity of main memory systems. Unfortunately, lower technology nodes worsen the cell reliability as it increases the coupling between adjacent DRAM cells, thereby exacerbating different failure modes. This paper investigates the reliability problem due to Row Hammering, whereby frequent activations of a given row can cause data loss for its neighboring rows. As DRAM scales to lower technology nodes, the threshold for the number of row activations that causes data loss for the neighboring rows reduces, making Row Hammering a challenging problem for future DRAM chips. To overcome Row Hammering, we propose two architectural solutions: First, Counter-Based Row Activation (CRA), which uses a counter with each row to count the number of row activations. If the count exceeds the row hammering threshold, a dummy activation is sent to neighboring rows proactively to refresh the data. Second, Probabilistic Row Activation (PRA), which obviates storage overhead of tracking and simply allows the memory controller to proactively issue dummy activations to neighboring rows with a small probability for all memory access. Our evaluations show that these solutions are effective at mitigating Row hammering while causing negligible performance loss (<; 1 percent).