Row Boundary Research Articles

VLSI Placement Optimization Algorithms

Placement is a fundamental optimization step to compute cell locations. The quality of results in Clock Tree Synthesis (CTS) and routing stages is impacted by the placement solution. The placement optimization flow is split into (1)global placement, (2) legalization, and (3) detailed placement. In global placement, cell locations are computed to minimize total wire length subject to a maximum cell density threshold. The cell overlapping and cell alignment to site row boundaries are relaxed. In legalization, cells are placed in locations free of overlapping and aligned to site row boundaries. Legalization algorithms compute cell locations with minimized cell displacement. In detailed placement, objectives are optimized locally. Detailed placement algorithms iterate over one cell or a small set of cells. The traditional optimization objective is total wire length. Placement algorithms also address timing violations, routability, design rules, and so forth. The placement algorithms rely on heuristics and formal methods to compute optimized cell locations. Moreover, placement algorithms require models to address signal delay propagation, area density, routing congestion, hyper-edge nets, and so forth. In the literature, several algorithms have been presented to improve placement solutions. On the other hand, placement is a really challenging problem that continues to have space for further improvement and for innovative algorithms.

Limited contiguous processor allocation mechanism in the mesh-connected multiprocessors using compaction

In this paper, several efficient migration and allocation strategies have been compared on the mesh-based multiprocessor systems. The traditional non-preemptive submesh allocation strategies consist of two row boundary (TRB) and two column boundary (TCB). The existing migration mechanisms are online dynamic compaction-four corner (ODC-FC), limited top-down compaction (LTDC), TCB, and the combination of TCB and ODC-FC algorithms. Indeed, the new allocation method is presented in this paper. This mechanism has the benefits of two efficient traditional allocation algorithms. It is the combination of the TCB and TRB allocation methods. Also, in this process the impact of four key metrics on online mapping is considered. The parameters are average task execution time (ATET), average task system utilization (ATSU), average task waiting time (ATWT), and average task response time (ATRT). Using TCB and TRB mechanism with the migration strategies is shown that the new algorithm has better ATET, ATRT, ATWT, and ATSU. It has, respectively, 23.5494, 97.1216, 39.1291, and 4.142% improvements in comparison with the previous mechanisms.

Performance Improvement in Multiprocessors using Two Row Boundary Allocation Method and Online Dynamic Compaction Algorithm

this paper, two row boundary (TRB) allocation algorithm and limited top-down compaction (LT-DC) migration method are proposed. The first scheme, attempts to allocate the free nodes in the center of the mesh and decrease the problem of external fragmentation. The next mechanism use task migration to improve the performance of existing sub-mesh allocation strategies. It should be noted that in this process three key metrics are considered. They are average execution time, average response time, and average wait time. In fact, we perform rigorous simulation experiments based on practical workloads as reported in the literature to quantify all our proposed schemes and compare them against standard schemes existing in the literature. Based on the results, we make clear recommendations on the choice of the strategies.

Asymptotic solution of the Nernst-Planck-Poisson-Stokes set near a surface with selective properties

The asymptotic approach (5) to the solution of a twodimensional problem taking into account the hydrodynamics is based, in particular, on the assump� tion that the variation of unknowns along the mem� brane surface is slow in comparison with the variations along the transverse direction. In (5) the assumptions (3) were used and the expression for the slippage veloc� ity at the region boundary with the subsequent use of this expression for solving the problem in the electri� cally neutral diffusion region is obtained. Such an approach proved to be incorrect. In (4) the solution was corrected by taking into account the effect of nar� row boundary layers. The assumption about the slow� ness of variations along the membrane was left without change.

Mixed block placement via fractional cut recursive bisection

Recursive bisection is a popular approach for large scale circuit placement problems, combining a high degree of scalability with good results. In this paper, we present a bisection-based approach for both standard cell and mixed block placement; in contrast to prior work, our horizontal cut lines are not restricted to row boundaries. This technique, which we refer to as a fractional cut, simplifies mixed block placement and also avoids a narrow region problem encountered in standard cell placement. Our implementation of these techniques in the placement tool Feng Shui 2.6 retains the speed and simplicity for which bisection is known, while making it competitive with leading methods on standard cell designs. On mixed block placement problems, we obtain substantial improvements over recently published work. Half perimeter wire lengths are reduced by 29% on average, compared to a flow based on Capo and Parquet; compared to mPG-ms, wire lengths are reduced by 26% on average.

Parallelization of the Hoshen-Kopelman Algorithm Using a Finite State Machine

In applications such as landscape ecology, computer mod eling is used to assess habitat fragmentation and its ecological implications. Maps (two-dimensional grids) of habitat clusters or patches are analyzed to determine the number, location, and sizes of clusters. Recently, improved sequential and parallel implementations of the Hoshen- Kopelman cluster identification algorithm have been designed. These implementations use a finite state ma chine to reduce redundant integer comparisons during the cluster identification process. The sequential implementa tion for large maps performs cluster identification by par titioning the map along row boundaries and merging the results of the partitions. The parallel implementation on a 32-processor Thinking Machines CM-5 provides an effi cient mechanism for performing cluster identification in parallel. Although the sequential implementation achieved promising speed improvements ranging from 1.39 to 2.00 over an existing Hoshen-Kopelman implementation, the parallel implementation achieved a minimum speedup of 5.41 over the improved sequential implementation, exe cuted on a Sun SPARCstation 10.

A floating-gate MOS learning array with locally computed weight updates

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 /spl mu/s, whereas the weight normalization takes minutes to hours.