Routing Tools Research Articles

A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 $\times$ 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits.

A transportation network assessment tool for hazardous material cargo routing: Weighing exposure health risks, proximity to vulnerable areas, delay costs and trucking expenses

The inherent risks associated with accidental releases of hazardous materials during transport have drawn attention and concerns in the recent decades. The aim of this study is to propose a tool for evaluation and comparison of the transportation networks which can be used to assess the routing options between origins and destinations of the cargos for their suitability for transporting hazardous material cargos by tanker trucks and to identify routes which provide lower accidental release risks, lower public exposure risks, and offer economical benefits. Each route segment of transportation networks were evaluated using specific criteria which included health risk and cost of delay in case of an accidental release of materials, trucking cost and proximity to vulnerable areas. Since, the health impact of hazardous materials differ depending on the characteristics of the material being transported as well as release quantities and atmospheric conditions; this paper aimed in providing a tool that can be used to estimate the impact radius (for health risks) after accidental release of hazardous materials by taking into account different atmospheric conditions based on the meteorological data and solar elevation angle. The Gaussian air dispersion model paired with ArcGIS using Python programming were employed to estimate the health risk impact zones by considering the meteorological data, and accordingly to analyze road segments for cost impacts (delay and trucking costs), and the proximity to vulnerable areas. The route assessment tool was demonstrated with a case study. The results of this study can efficiently aid decision makers for transportation of hazardous materials.

Evaluation of Munich's Cycle Route Planner Data Analysis and Customer Survey

A convenient combination of pre- and on trip route information for cyclists are online routing tools. The Munich Transport and Tariff Association in cooperation with the Department of Environment and Health recently developed the MVV Cycle Route Planner. This online route-planning tool can be used either on desktop computers or on smartphones and covers the greater Munich region based on Open Street Map Data. It enables both users and municipalities to add information of cycle routes and other new bicycle infrastructure to the route planner and improve the system continuously. It provides a navigation and map service especially for the requirements of cyclists and can be combined with the use of public transport. This paper concentrates on three different research approaches. In a data analysis more than 130.000 single requests from April until August 2015 were examined with focus on the spatial distribution of origins and destinations in Munich and the suburban region. As a result, the demand and frequency of the user requests give a strong lead where cycle flows are to be expected and further infrastructure, like cycle super highways or improved cycle routes, needs to be considered. A customer survey of users and non-users revealed their mobility patterns and the actual use of the cycle route planner for trips to work or for leisure. The survey focused on usage and assessment of the cycle route planner itself. It further analyzed which means of transport are used for frequent trips and what the restrictions are so far, not to use the bicycle.

PROTON+

Optical Networks-on-Chip (ONoCs) are a promising technology to overcome the bottleneck of low bandwidth of electronic Networks-on-Chip. Recent research discusses power and performance benefits of ONoCs based on their system-level design, while layout effects are typically overlooked. As a consequence, laser power requirements are inaccurately computed from the logic scheme but do not consider the layout. In this article, we propose PROTON+, a fast tool for placement and routing of 3D ONoCs minimizing the total laser power. Using our tool, the required laser power of the system can be decreased by up to 94% compared to a state-of-the-art manually designed layout. In addition, with the help of our tool, we study the physical design space of ONoC topologies. For this purpose, topology synthesis methods (e.g., global connectivity and network partitioning) as well as different objective function weights are analyzed in order to minimize the maximum insertion loss and ultimately the system’s laser power consumption. For the first time, we study optimal positions of memory controllers. A comparison of our algorithm to a state-of-the-art placer for electronic circuits shows the need for a different set of tools custom-tailored for the particular requirements of optical interconnects.

R.randomwalk v1, a multi-functional conceptual tool for mass movement routing

Abstract. We introduce r.randomwalk, a flexible and multi-functional open-source tool for backward and forward analyses of mass movement propagation. r.randomwalk builds on GRASS GIS (Geographic Resources Analysis Support System – Geographic Information System), the R software for statistical computing and the programming languages Python and C. Using constrained random walks, mass points are routed from defined release pixels of one to many mass movements through a digital elevation model until a defined break criterion is reached. Compared to existing tools, the major innovative features of r.randomwalk are (i) multiple break criteria can be combined to compute an impact indicator score; (ii) the uncertainties of break criteria can be included by performing multiple parallel computations with randomized parameter sets, resulting in an impact indicator index in the range 0–1; (iii) built-in functions for validation and visualization of the results are provided; (iv) observed landslides can be back analysed to derive the density distribution of the observed angles of reach. This distribution can be employed to compute impact probabilities for each pixel. Further, impact indicator scores and probabilities can be combined with release indicator scores or probabilities, and with exposure indicator scores. We demonstrate the key functionalities of r.randomwalk for (i) a single event, the Acheron rock avalanche in New Zealand; (ii) landslides in a 61.5 km2 study area in the Kao Ping Watershed, Taiwan; and (iii) lake outburst floods in a 2106 km2 area in the Gunt Valley, Tajikistan.

Development of Digital Application Specific Printed Electronics Circuits: From Specification to Final Prototypes

This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i.e., PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested.

Mathematical model for flood routing based on cellular automaton

Increasing frequency and severity of flooding have caused tremendous damage in China, requiring more essential countermeasures to alleviate the damage. In this study, the dynamic simulation property of a cellular automaton was used to make further progress in flood routing. In consideration of terrain's influence on flood routing, we regarded the terrain elevation as an auxiliary attribute of a two-dimensional cellular automaton in path selection for flood routing and developed a mathematical model based on a cellular automaton. A numerical case of propagation of an outburst flood in an area of the lower Yangtze River was analyzed with both the fixed-step and variable-step models. The results show that the flood does not spread simultaneously in all directions, but flows into the lower place first, and that the submerged area grows quickly at the beginning, but slowly later on. The final submerged areas obtained from the two different models are consistent, and the flood volume balance test shows that the flood volume meets the requirement of the total volume balance. The analysis of the case shows that the proposed model can be a valuable tool for flood routing.

A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise

Analog layout design has been a manual, time-consuming, and error-prone task for decades. To speed up layout design time for a new design, analog layout designers prefer referring to legacy designs and layouts rather than starting from scratch, or thoroughly applying placement and routing tools because legacy layouts contain pretty much design expertise. Motivated by such layout design process, this paper presents the first knowledge-based physical synthesis methodology to generate new layouts by integrating existent design expertise. The proposed approach can automatically analyze legacy design data including circuits, layouts, and constraints, extract matched sub-circuits between new and legacy designs, and generate multiple layouts for the new design by utilizing the quality-approved legacy layouts as much as possible. Experimental results show that the proposed methodology can achieve high layout reusage rate, and hence the designers' layout preference can be successfully reserved.

Traffic Route Modelling and Assignment with Intelligent Transport System

Abstract The development of signal transmitting environment for multimodal traffic control will enhance the integration of emergency and specialized transport routing tools in usual traffic control paradigms - it is one of the opportunities offered by modern intelligent traffic control systems. The improvement of effective electric power use in public transport system is an advantage of Intelligent Transport System (ITS). The research is connected with the improvement of on-line traffic control and adaptation of special traffic lighting alternatives by ITS. The assignment of the nearest appropriate transport will be done by passenger request, but unlike information system, the transport planning is done on demand. The task can be solved with the help of modern technical methods and equipment, as well as by applying control paradigms of the distributed systems. The problem is solved with the help of calculations hyper-graph and scheduling theory. The goal of the research is to develop methods, which support scheduling of the emergency transport, using high performance computing.

A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic

We present a new approach for gate-level delay-insensitive asynchronous logic. The new approach uses only conventional synchronous synthesis and computer-aided design tools, as well as conventional standard cell libraries. This new design approach is highly suitable for very low voltage operation compared with traditional static CMOS design. An auto-sleep mode together with supply voltage control logic reduces leakage power consumption. Several benchmark circuits are implemented using IBM 130nm technology to show that the new asynchronous logic approach is robust even when operating in the sub-threshold regime. The layout for each benchmark is generated using Cadence's automatic placement and routing tool. Hspice simulations for both asynchronous and synchronous versions of the benchmark circuits enabled comparison of the delay, area and leakage current. Monte Carlo simulations are performed for each benchmark circuit to demonstrate delay insensitivity for very low supply voltages with substantial threshold voltage ($$V_{T}$$VT) variations.

Single-Event-Upset Mitigation Placement and Routing Algorithms for Field-Programmable Gate Arrays

To reduce the effects of single-event upsets (SEUs) on field-programmable gate arrays (FPGAs), we propose anti-VPR, an anti-SEU algorithm. The Anti-VPR algorithm is based on VPR, a popular placement and routing tool. The proposed algorithm optimizes the FPGA place cost function and reduces the occurrence of errors, such as open circuit error and short circuit error, by computing the error propagation probability and node error rate of the Configurable Logic Blocks. The Anti-VPR algorithm is implemented and tested on several MCNC benchmark circuits. Experimental results show that the proposed Anti-VPR algorithm achieves a 36.2% greater reduction of sensitive bits compared with the original VPR algorithm without the need for extra hardware overhead, unlike the traditional TMR approach.

Incorporating transmission losses in flash flood routing in ephemeral streams by using the three-parameter Muskingum method

Stream flow in arid and semi-arid regions is usually in a form of flash floods that occur in dry bed ephemeral streams. In this research, the three-parameter Muskingum method has been investigated as a tool for flash flood routing in arid zones using data from Yiba catchment in the Kingdom of Saudi Arabia. The method is general; it takes into account both lateral inflows from side tributaries and also lateral outflow which can represent transmission losses. Applying the methodology for ephemeral streams requires some modifications of the assumptions. The ephemeral stream is considered as a long linear channel with a total movement time of the hydrograph that consists of two parts, the translation time and the redistribution time. The translation time is the travel time of the flood between two stations, while the redistribution time is the lag time that is estimated from the conventional Muskingum method due to the reshaping of the hydrograph. Eight runoff events have been studied for the model parameter estimation phase, while another four events are considered for the verification phase. A spreadsheet model has been developed to implement the methodology and checked with data from the published literature. The method shows very good results; the average RMSE value is 3 m3/s for the hydrographs of the reconstructed events. The correlation coefficients between observed and calculated parameters show relatively high correlation, i.e., 0.99 for the peak discharges, 0.95 for the time lags, and 0.99 for coefficient of transmission losses (the α-parameter). The maximum transmission loss is estimated to be 84 % of the inflow hydrograph form the studied events. A Monte Carlo approach is followed for the verification of the model. It has been found out that the following set of combination of the routing parameter, i.e., a lower limit of d 1, an upper limit of d 2 and a lower limit of d 3 produces satisfactorily good results for the four independent events. Results indicate that the three-parameter Muskingum method exhibits good results in simulating flash flood routing in arid environments.

Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This article describes our novel masked dual-rail pre-charged memory approach, called “intra-masking dual-rail memory (IMDRM) on LUT”, and its implementation on FPGA for Side-Channel Attack-resistant (SCA-resistant) AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and parts of dual-rail memory with unsafe buses (buses that are not masked) are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. Inputs and outputs of all LUTs are masked, and so can be considered safe signals. Several LUTs can be combined to create a safe SBox. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced SCA-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

Relationships between Methods for Presenting Information on Navigation Tools and Users' Wayfinding Behavior

This study examines the effects of different methods for presenting navigational information on users' wayfinding behavior and spatial memory. In the first experiment, we examined tools that differed in the degree to which they induced the user to engage in deliberate route planning. We found that users of a tool that showed a route to the goal (the route tool) had a poor scene-recognition memory and simply followed the directed route, compared to users of a paper map which did not show a route. A tool that showed the direction toward the goal (the direction tool) was equivalent to the route tool with respect to users’ scene-recognition memory, but allowed users to take routes more varied than the route tool and as varied as the paper map did. The direction tool affected men and women differently, inducing the latter to make more turns. Our second experiment examined the effects of the size of the device screen, and found that the map’s advantage of allowing the user to attend to their surroundings diminished when the map was shown in small size. We discuss implications for designing effective navigational aids in different situations.

Hall Effect Gyrators and Circulators

The electronic circulator, and its close relative the gyrator, are invaluable tools for noise management and signal routing in the current generation of low-temperature microwave systems for the implementation of new quantum technologies. The current implementation of these devices using the Faraday effect is satisfactory, but requires a bulky structure whose physical dimension is close to the microwave wavelength employed. The Hall effect is an alternative non-reciprocal effect that can also be used to produce desired device functionality. We review earlier efforts to use an ohmically-contacted four-terminal Hall bar, explaining why this approach leads to unacceptably high device loss. We find that capacitive coupling to such a Hall conductor has much greater promise for achieving good circulator and gyrator functionality. We formulate a classical Ohm-Hall analysis for calculating the properties of such a device, and show how this classical theory simplifies remarkably in the limiting case of the Hall angle approaching 90 degrees. In this limit we find that either a four-terminal or a three-terminal capacitive device can give excellent circulator behavior, with device dimensions far smaller than the a.c. wavelength. An experiment is proposed to achieve GHz-band gyration in millimetre (and smaller) scale structures employing either semiconductor heterostructure or graphene Hall conductors. An inductively coupled scheme for realising a Hall gyrator is also analysed.

FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects

In this paper we introduce a novel field programmable gate array (FPGA) architecture with resistive random access memory (RRAM)-based programmable interconnects (FPGA-RPI). Programmable interconnects are the dominant part of FPGA. We use RRAMs to build programmable interconnects, and optimize their structures by exploiting opportunities that emerge in RRAM-based circuits. FPGA-RPI can be fabricated by the existing CMOS-compatible RRAM process. Using an advanced placement and routing tool named VPR-RPI which was developed to deal with the novel architecture, a customized CAD flow is provided for FPGA-RPI. Results show that the programmable interconnects of FPGA-RR have a 96% smaller footprint, 55% higher performance, and 79% lower power consumptions compared to other FPGA counterparts.

TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network

Dynamic partial reconfiguration of FPGAs enables the dynamic specialization of the circuit for the runtime needs of the application. Previously a tool flow, called the TLUT tool flow, was developed to aid the designer in applying dynamic circuit specialization (DCS) for their designs. The TLUT tool flow generates an implementation in which the lookup tables (LUTs) can be specialized during runtime. In this paper, place and route algorithms are described for the TCON tool flow. The TCON tool flow generates implementations in which not only the logic infrastructure (LUTs) is dynamically specialized, but also the routing infrastructure of the FPGA. Exploiting the reconfigurability of the FPGA interconnection network further improves area (50% to 92% less LUTs and 36% to 81% less wiring), logic depth (a 63% to 80% reduction) and power consumption. To achieve this, major changes were needed, not only in the mapping, but also in the place and route steps. This work describes the altered place and route algorithms, called TPlace and Troute.

Efficient Allocation of Electric Vehicles Charging Stations: Optimization Model and Application to a Dense Urban Network

The deployment of Electric Vehicles (EVs) needs an optimized and cost-effective implementation of charging stations. As a decision support tool for network design, we define a methodology to allocate charging stations in a real network. This study uses trip OD matrix information from household travel survey coupled with a dynamic vehicle model to evaluate EVs consumption based on realistic trips (urban drive cycles). These trips are computed based on routing tools and supplied with elevation information. This enables an accurate characterization of energy needs in the Lyon Metropolitan Area. All these parameters are used as inputs of an integer linear optimization program for the location of charging stations. The methodology is based on an adaption of the classic fixed charge location model with a p-dispersion constraint. The results indicate that this methodology can help the future implementation of charging stations at an urban scale.

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning

A structured ASIC, one kind of programmable logic device (PLD), consists of a homogeneous array of programmable logic elements, or called tiles. The architecture of each tile is supposed to be very general so that any kind of logic can be implemented on it; this is the main reason why a structured ASIC has an inherently limited performance, together with a large area requirement compared to an ASIC. This balances the little mask cost of structured ASIC. We tilt this balance by introducing a small number of different types of tile, each with its own architecture, which can be deployed across different designs by the use of a simple blocking mask. This is made possible by a new photolithography concept called selectively patterned masks (SPM), which we propose. We address the practical issues of SPM, including mask cost and manufacturing time. We introduce the heterogeneous array of programmable logic (HAPL), which is a new structured ASIC which takes advantage of SPM. HAPL has its own tile and routing architectures, and supporting CAD tools for packing and routing. Extensive experiments in 45-nm technology are used to assess HAPL and compare it with ASIC. A HAPL design that is optimized for area is about twice the size of its ASIC counterpart. A delay-optimized HAPL design exhibits a post-layout delay which is, on average, 1.35 that of an equivalent ASIC.

Development and Evaluation of Learner-centric Graphical Educational Tool for IP Routing and Network Behavior

Development and Evaluation of Learner-centric Graphical Educational Tool for IP Routing and Network Behavior