TSV based 3D stacking IC technology has been aggressively studied recently because of strong benefits in terms of significantly form factor shrinkage, superior system performance (bandwidth & speed), great power reduction, and heterogeneous integration capability. According to different applications, there are different integration options for TSV processing. For high performance 3D system applications which required fine TSV pitch and massive IO connections, how to establish a proper TSV integration scheme became a key importance of enabling 3D IC commercialization. In additional to common foundry used via-middle (VM) process, two another via last approaches, either forming TSV form front-side or backside were also been considered as major TSV process schemes. Although front-side via last (FVL) TSV is widely adopted by OSATs, this scheme is inherently not suitable for fine pitch and high density TSV applications because of significant area penalty and wire routing constraint comparing to VM TSV process. Another backside via last (BVL) TSV process, however, showed many advantages over common VM TSV process while achieving same TSV scalability/density and routing flexibility. For examples: (1) Cu TSVs of BVL were formed after completely CMOS FEOL+BEOL processes, thus it is naturally much less or no Cu pumping out induced yield loss issues comparing to VM process; (2) BVL TSV etching can be stopped on front-side metal 1 layer instead of time etching in blind TSV of VM scheme; (3) No complicated and yield sensitive backside Cu reveal issue were involved; (4) TSV & RDL can be formed together via dual-damascene like processing to simplify process flow and reduce cost of ownership; (5) BVL process can be adopted by either foundry or OSAT manufacturers resulting in most flexible business model in 3DIC supply chain. Despite of the vantage of backside via-last scheme, many process challenges still need to be solved. In this paper, key issues of via middle integration were briefly reviewed. A capable of high aspect ratio and fine pitch TSV (CD … 5um) manufacture scheme was proposed via backside via last integration scheme. Key process technologies and challenges of this BVL scheme, such as temporary bonding, glue material selection, wafer thinning, backside TSV formation, CMP planarization as well as cost reduced TSV/RDL dual damascene flow are investigated.