Robust Path Delay Fault Testability Research Articles

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design, and uses only 2-input AND-OR gates. A universal test set of size (n2/8 + 3n/4) for detecting all single stuck-at faults can be easily determined for an n-input module, where n = 2k, k � 3. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees full robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those of earlier designs. Results on circuit area and delay for a few benchmark examples are also reported.

Synthesis of symmetric functions for path-delay fault testability

A new technique of synthesizing totally symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit can be made robustly path-delay fault testable, if the constituent unate functions are synthesized as two-level irredundant circuits. Nonconsecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The circuit cost of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results shows that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn, reduces testing time, as compared to those of the best-known earlier methods.

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we introduce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.

Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability

In this paper, we present methods for synthesis of sequential circuits for easy testability based on a scheme previously referred to as synthesis for parallel scan. A heuristic is used to achieve maximal merging of the testability logic with the normal combinational logic of the sequential circuit in order to minimize the area overhead. The latches used in the proposed scheme are normal nonscan latches. The synthesis for parallel scan scheme is applied to two different fault models. To facilitate stuck-at-fault testability of sequential circuits, the synthesis for parallel scan method is augmented with a novel structural analysis technique for selection of latches for partial scan with emphasis on minimization of delay overhead. Experimental results on ISCAS '89 benchmarks resynthesized by our method indicate that one can, in general, achieve the same level of testability with less area and delay overheads, as compared to the conventional structural analysis method for partial scan. A method for synthesizing fully hazard-free robust path-delay fault testable sequential circuits using the concept of synthesis for parallel scan is also presented. When the number of primary inputs of the sequential circuit is at least as large as the number of latches, only normal nonscan latches are required. Experimental results on MCNC and ISCAS '89 benchmarks show the area overheads to be very reasonable. No previous method could ensure complete robust testability of all path-delay faults in a sequential circuit without assuming a completely enhanced scan, even under the above condition. However, when this condition is not met, i.e., the number of primary inputs is less than the number of latches, we introduce the concept of synthesis for maximally parallel enhanced scan. This still provides complete robust testability, however, at the expense of a higher area overhead.

Delay-fault testability preservation of the concurrent decomposition and factorization transformations

Recently, a new, very efficient method of multilevel logic synthesis based on factorization and decomposition of Boolean expressions has been introduced. It has been shown that the transformations used by this method preserve the single stuck-at testability of two-level circuits. This paper shows that single-cube extraction, double-cube extraction, and dual-extraction of double-cubes/spl isin/D/sub 1,1,2/ and D/sub 2,2,2/ preserve testability with respect to a general robust path-delay-fault (RPDF) test set. However, the authors show that while dual-extraction of double-cubes/spl isin/D/sub 2,2,3/ preserves RPDF testability of paths through the extracted divisors with respect to a single-input-changing test set, it does not guarantee RPDF testability preservation of unmodified paths. Furthermore, the authors provide sufficient conditions for algebraic resubstitution with complement to preserve RPDF testability that cover a larger class of complementary expressions than was known previously. The testability preservation of these transformations is demonstrated on a set of RPDF testable Berkeley PLAs. >

Synthesis for path delay fault testability via tautology-based untestability identification and factorization

An area efficient synthesis procedure targeting complete robust path delay fault testability (RPDFT) of scan-based circuits is described. It includes an efficient untestability identification algorithm for two-level and multilevel circuits. The implementation of the algorithm uses tautology checking instead of test pattern generation (TPG) resulting in a speed-up factor of 5 in comparison to today's fastest TPG methods. Exploiting that untestability identification capability, factorization is improved to first combining only those product terms in which the same literal is untestable and checking whether this eliminates the untestable fault. If not, cardinality matching is used to add the best-suited term that removes the untestable fault. Our method has been found to give better results in terms of RPDFT and area than reported before. In contrast to previously published papers, we found that technology mapping using tree covering does not always preserve RPDFT.