Synthesis for path delay fault testability via tautology-based untestability identification and factorization

Abstract

An area efficient synthesis procedure targeting complete robust path delay fault testability (RPDFT) of scan-based circuits is described. It includes an efficient untestability identification algorithm for two-level and multilevel circuits. The implementation of the algorithm uses tautology checking instead of test pattern generation (TPG) resulting in a speed-up factor of 5 in comparison to today's fastest TPG methods. Exploiting that untestability identification capability, factorization is improved to first combining only those product terms in which the same literal is untestable and checking whether this eliminates the untestable fault. If not, cardinality matching is used to add the best-suited term that removes the untestable fault. Our method has been found to give better results in terms of RPDFT and area than reported before. In contrast to previously published papers, we found that technology mapping using tree covering does not always preserve RPDFT.