BDD based synthesis of symmetric functions with full path-delay fault testability

Abstract

A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. BDDs are used for the synthesis step. Only one additional input and one inverter are needed to achieve 100% Path Delay Fault (PDF) testability. The size of the circuit is guaranteed to be at most quadratic in the number of inputs. The test vectors for any PDF can be generated in linear time. Experimental results underline the efficiency of the technique. In contrast to previous approaches, the technique can also be applied to multi-output functions.