RMS Phase Error Research Articles

A 27–42-GHz Low Phase Error 5-Bit Passive Phase Shifter in 65-nm CMOS Technology

A 27-42-GHz 5-bit passive switching phase shifter is presented using 65-nm CMOS technology for the fifth generation (5G) applications. In the 180° phase shift bit, a reflection-type-based biphase modulator topology is developed to achieve good phase shifting performance over a wide bandwidth. The measured insertion loss (IL) of all 32 states is 12.4 ± 1.2 dB at 39 GHz and 11.4 ± 2.3 dB at 28 GHz with zero dc power. The phase shifter demonstrates an ultralow root mean square (rms) phase error of 0.7° and a low rms amplitude error of 0.8 dB at 37 GHz with an inherent digital phase-control mechanism. The rms phase error is less than 3.8° and the rms amplitude error is less than 2.1 dB from 27 to 42 GHz.

Single-shot characterization of strongly focused coherent XUV and soft X-ray beams.

In this Letter, we present a novel, to the best of our knowledge, single-shot method for characterizing focused coherent beams. We utilize a dedicated amplitude-only mask, in combination with an iterative phase retrieval algorithm, to reconstruct the amplitude and phase of a focused beam from a single measured far-field diffraction pattern alone. In a proof-of-principle experiment at a wavelength of 13.5 nm, we demonstrate our new method and obtain an RMS phase error of better than λ/70. This method will find applications in the alignment of complex optical systems, real-time feedback to adaptive optics, and single-shot beam characterization, e.g., at free-electron lasers or high-order harmonic beamlines.

A 56-to-66 GHz CMOS Low-Power Phased-Array Receiver Front-End With Hybrid Phase Shifting Scheme

This paper presents a millimeter-wave phased-array receiver front-end with compact size and low-power consumption. A combination of local oscillator (LO) and radio frequency (RF) phase-shifting schemes is used to reduce the power consumption and RF path loss. Moreover, in the implementation of active circuits, a bulk isolation technique is used to achieve a higher power gain with a minimum number of stages. This technique is also utilized in the RF path phase shifter switches to mitigate the loss. To validate the proposed architecture, a single-element 56-to-66 GHz phased-array receiver front-end is fabricated in a 65-nm bulk CMOS process. Based on the measurement results, the receiver achieves a power gain of ~14.85 dB and a minimum noise figure (NF) of 5.7 dB. The measured average RMS phase and gain errors are ~3.5° and ~0.45 dB, respectively. The input 1-dB compression point ( $\text{P}_{\mathrm {-1dB}}$ ) of the receiver chain is about −19 dBm. The complete receiver, including active balun and required buffers (excluding the LO), consumes ~50 mW from a 1-V power supply and excluding the pads occupies a silicon area of 0.93 mm2.

A 3–6-GHz Wideband Compact 6-Bit Phase Shifter in 0.5-μm GaAs Technology

This letter presents a 3-6-GHz wideband compact 6-bit phase shifter (PS) in 0.5-μm GaAs pHEMT process. It combines a 3-bit enhanced high-pass/low-pass topology, a 2-bit modified low-pass/resonator topology, and a 1-bit switched-filter structure, with optimized cascade order to achieve a bandwidth (BW) up to 66.7%. Since the proposed PS consists of lumped elements and minimized the number of switches and inductors, it achieves a compact core size of 1.214 mm2. The 64-output state PS exhibits high phase resolution of 5.625° with an rms phase error (PE) of less than 4°, and an insertion loss (IL) less than 6.7 dB at 3-6 GHz. To the best of our knowledge, this PS achieves the largest BW with the smallest chip size among the published 5-bit/6-bit GaAs/GaN PSs over a similar band.

A 37–40-GHz Low-Phase-Imbalance CMOS Attenuator With Tail-Capacitor Compensation Technique

A Ka-band 5-bit CMOS digital step attenuator (DSA) with low phase variations for 5G applications is presented. The attenuator cell is optimized to alleviate the phase variations of conventional switched attenuators. A tail capacitor that is connected in series with the shunt resistor is used to construct a correction network with hyperbolic function characteristics. The DSA was implemented using a 65 nm CMOS process. It has a maximum attenuation range of 31 dB with 1.0 dB steps. With the help of the tail capacitor, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.27 dB and a rms phase error less than 3.7° from 37-40 GHz, the lowest such errors ever reported. The active core layout area is 0.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.51 mm × 0.42 mm). It shows suitable performance for 5G applications. The DSA is integrated into a phase-/amplitude-controlling chip to constitute a 5G system.

A K‐band fully differential 4‐channel transmitter IC in 65 nm CMOS technology

AbstractA K‐band 4‐channel transmitter IC with fully differential architecture is presented in this paper for beamforming phased‐array system. This IC uses commercial 65 nm CMOS technology. The major building blocks of this IC are 3‐stage medium power amplifiers (MPAs) with resistive feedback network to control the gain, 6‐bit phase shifter with tuning bit, 15 dB attenuators, 4‐way power divider consisting switches, and a Marchand balun. All above components are designed by differential architecture. The cross‐connected switch type 180° phase shifter and the differential 4‐way power divider is implemented for low insertion loss and small chip size compared with its conventional switched type phase shifter and three differential 2‐way power dividers, respectively. This TX IC has −5 dB overall gain at 21‐23 GHz. Furthermore, it also available phase shifting of 360° with 5.6° step and attenuating of 29 dB with 1 dB step at 21‐23 GHz, respectively. The RMS phase errors and the RMS amplitude error are achieved &lt;3° and &lt;1 dB at 21‐23 GHz, respectively. The achieved P1dB and saturation power (PSAT) of this TX IC are &gt;0 dB m and &gt;6 dB m, respectively. The 4‐channel TX IC consumes 140 mA of DC current at 2.5 V supply voltage. The overall dimension of 4‐channel TX IC is 3 × 1 mm2.

High Resolution Reconfigurable Phase-Tuning Line Using Self-Shielded 3-D Interdigital Capacitor

A compact high-resolution reconfigurable phase-tuning line (RPTL) based on self-shielded 3-D interdigital capacitors is presented in this letter. Such a capacitor with high- $Q$ and self-shielded characteristics is used to implement the digitally switchable capacitor array in the RPTL, which is integrated with a coplanar waveguide and can lead to merits of the low loss, high phase-tuning resolution, and compact size. Meanwhile, the grounded shield is utilized in the RPTL to further reduce the loss. To verify the mechanisms of aforementioned structure, a 6-bit digital controlled RPTL is implemented and fabricated using a 40-nm CMOS technology. At 30 GHz, the measured loss of the proposed RPTL is 2.1 dB, while a tuning resolution of 0.38° with an RMS phase error of 0.25° is achieved.

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS

This article presents the first 39-GHz phased-array transceiver (TRX) chipset for fifth-generation new radio (5G NR). The proposed transceiver chipset consists of 4 sub-array TRX elements with local-oscillator (LO) phase-shifting architecture and built-in calibration on phase and amplitude. The calibration scheme is proposed to alleviate phase and amplitude mismatch between each sub-array TRX element, especially for a large-array transceiver system in the base station (BS). Based on LO phase-shifting architecture, the transceiver has a 0.04-dB maximum gain variation over the 360° full tuning range, allowing constant-gain characteristic during phase calibration. A phase-to-digital converter (PDC) and a high-resolution phase-detection mechanism are proposed for highly accurate phase calibration. The built-in calibration has a measured accuracy of 0.08° rms phase error and 0.01-dB rms amplitude error. Moreover, a pseudo-single-balanced mixer is proposed for LO-feedthrough (LOFT) cancellation and sub-array TRX LO-to-LO isolation. The transceiver is fabricated in standard 65-nm CMOS technology with flip-chip packaging. The 8TX-8RX phased-array transceiver module 1-m OTA measurement supports 5G NR 400-MHz 256-QAM OFDMA modulation with -30.0-dB EVM. The 64-element transceiver has a EIRPMAX of 53 dBm. The four-element chip consumes a power of 1.5 W in the TX mode and 0.5 W in the RX mode.

A K-Band 5G Phased Array RX Channel With 3.3-dB NF and 28.5-dB Gain in 130-nm SiGe

This brief presents a low-noise K-band phased array receive channel implemented in a 130-nm SiGe BiCMOS process. The IC consists of a cascode LNA, a vector modulator phase shifter (PS), and a current-steering VGA. The LNA employs a shunt inductor at the intermediate node of the cascode for noise reduction purposes. The PS generates I/Q signals by lumped quadrature hybrids for low noise operation. Various process compensation capabilities are employed within the PS to reliably achieve high resolution. The measured results demonstrated a peak gain of 28.5 dB at 24 GHz with a 3-dB bandwidth of 22–27 GHz. The measured noise figure is 3.3 dB, which is better than state-of-the-art among Si-based phased-array channels. For 6-b phase control, the rms phase error is 4° and 0.2° without and with calibration, respectively; the rms gain error being 1 dB for both cases. For 4-b gain control with 0.4-dB/step, the rms amplitude/phase errors are 0.1-dB/0.5°. Across different phase settings, the IC has an OP1dB of −2 to −3 dBm, with a power consumption of 48 mW. The total chip area is 1.33 mm2, excluding the pads.

A Compact Ka-Band 4-bit Phase Shifter With Low Group Delay Deviation

This letter presents a compact $Ka$ -band 4-bit switch-type phase shifter with low group delay deviation (GDD) using 28-nm CMOS technology. A magnetically coupled all-pass network (APN) configuration is employed to achieve both equal and flat group delay characteristics versus frequency at each phase state. The measured rms phase error is 1.2°, and the gain error is 1.1 dB at 33 GHz. The average measured insertion loss is 12.8 dB at 33 GHz, and the input and output return losses are both lower than −10 dB from 29 to 37 GHz. The fabricated phase shifter has a compact size of 0.08 mm2 excluding pads, low GDD of ±4 ps, and rms group delay error of $Ka$ -band phase shifter has the lowest GDD per bandwidth (GDD/BW) compared with other reported passive phase shifters.

A Full X-Band Phased-Array Transmit/Receive Module Chip in 65-nm CMOS Technology

In this paper, we present a phased-array transceiver chip operating in full X-band (8-12 GHz) in 65-nm CMOS technology. The presented transceiver for the transmit/receive module (TRM) consists of a 6-bit passive phase shifter, a 6-bit attenuator, a bi-directional gain amplifier (BDGA), and a single pole double throw (SPDT) switch connected to the internal power amplifier (PA) and the low-noise amplifier (LNA) to serve as a duplexer. A 64-bit SPI scan-chain is integrated for digital TRM control. The transmitter achieves greater than 15 dB of power gain with 11.84 dBm at the output 1-dB compression point (OP1dB). To achieve a wideband operation of the passive phase shifter, we assigned two different resonant frequencies for the phase leading and lagging networks and aligned the slopes of their phase responses to have the desired phase shifts at the center frequency. The RMS phase error is less than 5°, and the RMS amplitude error is less than 0.45 dB for all phase and attenuation states within 8-12 GHz while dissipating 216 mW dc power from a 1 V power supply. The receiver shows greater than 15 dB of power gain and has a noise figure (NF) of less than 8.4 dB for the entire X-band. The RMS phase error and the RMS amplitude error are less than 5° and 0.45 dB, respectively, for all control states within 8-12 GHz. The receiver consumes 110 mW with a 1 V power supply. The transceiver chip occupies an area of $4\times1.88$ mm 2 .

A Ku-Band 6-Bit Vector-Sum Phase Shifter With Half-Quadrant Control Technique

This paper presents a 6-bit vector-sum phase shifter with half-quadrant control technique for Ku-band phased arrays. In this paper, the gain and phase symmetry in each quadrant is studied. Based on the gain and phase symmetry in vector-sum phase shifter, the half-quadrant control technique is proposed to simplify the complexity of phase control, phase measurement and phase calibration for large-scale phased arrays. Besides, a phase optimization method without extra phase settings is proposed to achieve low phase error. As results, the measured 6-bit RMS phase error is 1.6° ~ 2.3° across 13 ~ 17 GHz with only 64 different phase states, demonstrating the brevity and accuracy of phase control simultaneously. With the same phase optimization, six chips are measured and the maximum deviation of RMS phase error is −11.4 dBm. The chip consumes 29.7 mW with 1.8 V supply and occupies $0.9\times1.45$ mm2. This work is fabricated in TSMC 180-nm CMOS technology.

A Ka-Band CMOS 4-Beam Phased-Array Receiver With Symmetrical Beam-Distribution Network

This letter demonstrates a Ka-band 4-beam phased-array receiver in 65-nm CMOS. To generate four balanced beams from two inputs, a passive 4-beam symmetrical differential network is employed to achieve balanced signal distribution. With the use of passive vector-modulated phase shifter and switched-type attenuator, the receiver consumes a current of only 40 mA under 1-V supply voltage. The 4-beam receiver shows 3-dB gain per channel. From 27 to 31 GHz, the RMS gain error and phase error are $2.6\times4$ mm2 with pads included. To author’s knowledge, this letter reports the first CMOS phased-array receiver with four balanced beams.

A Frequency-Reconfigurable CMOS Active Phase Shifter for 5G mm-Wave Applications

This brief presents an analog mm-wave active phase shifter utilizing a frequency-reconfigurable vector-summing topology. A frequency-tunable I/Q signal generator followed by frequency-tunable single-to differential convertors and variable gain amplifiers is employed to build the phase shifter. The designed phase shifter can be switched to operate over 24-30 GHz band or 35-41 GHz band. The phase shifter, fabricated in 90 nm CMOS technology, provides 360° of phase shifting range in both frequency bands while consuming only 17.6 mW of power and 0.34 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area (excluding pads). Measurement results show that the phase shifter's RMS phase errors for 32 phase states are less than 4° and 5.1° over 24-30 GHz band and 35-41 GHz band, respectively. RMS amplitude errors of the phase shifter for 32 measured phase states are less than 0.6 dB and 0.35 dB over the lower and higher operation bands, respectively. The measured input 1 dB compression points are larger than -2.8 dBm and -3.7 dBm over the lower and higher operation bands, respectively. The proposed phase shifter, which is able to cover the released frequency bands of n257, n258 and n260, is a good candidate for 5G mm-wave applications.

A 14–50-GHz Phase Shifter With All-Pass Networks for 5G Mobile Applications

In this article, an ultra-broadband phase shifter (PS) with a 14–50-GHz bandwidth (defined by a phase error below 1/2 LSB) is presented to address the multiband requirements of 5G millimeter-wave (mm-wave) systems. The PS construction is based on all-pass networks (APNs), which have shown broad bandwidth capabilities in a lower frequency range. Aiming toward 5G mobile applications, the proposed 2-bit, 45° phase resolution PS was implemented in 0.25- $\mu \text{m}$ BiCMOS, manufactured, and measured, achieving an insertion loss of 7.4 ± 0.26 dB at 28 GHz and 10 ± 0.22 dB at 39 GHz, with an rms gain and phase error <0.27 dB and <4° from 24 to 30 GHz, respectively, and <0.33 dB and <6° from 37 to 43.5 GHz, demonstrating its capabilities to cover the 5G mm-wave spectrum.

A 40-GHz 4-Bit Digitally Controlled VGA With Low Phase Variation Using 65-nm CMOS Process

A 40-GHz variable gain amplifier (VGA) with 4-bit digital gain control and low phase variation is designed and fabricated on the 65-nm CMOS process. The digital gain control mechanism is achieved using the presented digital version current steering topology. The measured gain of the VGA is between 22 and 6 dB at 40 GHz with 16 different linear-in-decibel gain states. Using the proposed two-stage digital version current steering VGA phase compensation technique, the measured phase variation is 3.18° within a 16-dB gain control range (GCR) and the root mean square (rms) phase error is 0.89° at 40 GHz.

A W-Band 6-Bit Phase Shifter With 7 dB Gain and 1.35° RMS Phase Error in 130 nm SiGe BiCMOS

This brief presents a W-band 6-bit active phase shifter fabricated in $0.13~\mu \text{m}$ SiGe BiCMOS process. A wideband quadrature signal generator composed of a 90-degree hybrid and a pair of transformers is exploited for low insertion loss and superior balance. Conventional architecture used in gain control unit is replaced by a novel phase inverter-embedded variable gain amplifier to achieve a high gain and low complexity. In addition, a balun-first combiner with symmetrical layout is utilized at the output to keep as low the imbalance of I/Q paths as possible. The proposed phase shifter exhibits a record average gain of 7 dB at 79 GHz with a 3-dB bandwidth from 71.5 to 84.5 GHz. The variation of gain remains below 2.1 dB over 64 phase states. The measured RMS phase error is 1.35° at 78 GHz and remains below 3.5° from 72 to 82 GHz. The RMS gain error is measured to be 0.46 dB at 75 GHz and keeps less than 0.76 dB from 71 to 82 GHz. The measured input 1dB compression point amounts to −10 dBm. To the best of the author’s knowledge, this brief presents the lowest RMS phase error (1.35°) and the highest gain (7 dB) compared with the reported silicon-based W-band active phase shifters.

Research on the comprehensive performance of PrFeB magnets for synchrotron radiation and free electron laser

PrFeB magnets, which possess excellent magnetic properties at low temperatures, have important application value as cryogenic permanent magnet undulators for synchrotron radiation sources and free electron lasers. In this research study, several high-performance PrFeB magnets (P42H, P48SH, and P48UH) were prepared, and their performance was comprehensively examined, including evaluations of their magnetic properties, microstructures, uniformity, and stability. Next, their application prospects were analyzed and discussed. In China, the first cryogenic permanent magnet undulators (CPMUs) with P48SH magnets with 18 mm cycle lengths have been developed. When the temperature is 80 K and the gap is 6.0 mm, the magnetic field measurement results of the CPMU showed that the effective magnetic field peak was approximately 0.92 T, yielding an increase of 11.76% relative to operation at 300 K, with an RMS phase error of about 4.99°.

Millimeter wave balun design and optimization based on compensation matching capacitors and active S parameter

AbstractA balun design algorithm based on the compensation matching capacitors and the active S parameter is given in this paper. Compared with the inductor matching network, the compensation matching capacitors not only compensate the phase and the amplitude error of the balun, but also occupy a compact chip area. Considering the coupling between two differential terminals of the balun, the active S parameter is adopted. On the basis of the active S parameter, the reflection coefficients of two differential terminals are calculated directly. On the basis of this algorithm, the simulated phase error and the amplitude error of the balun are less than 0.97° and 0.13 dB, from 15 to 18 GHz. Moreover, a 5‐bit differential switch‐type phase shifter with two baluns is designed in the 180‐nm complementary metal oxide semiconductor (CMOS) process at Ku band. Thanks to the small phase error of two baluns, the tested RMS phase error is less than 4°, from 15 to 18 GHz.

A 60-GHz Four-Element Beam-Tapering Phased-Array Transmitter With a Phase-Compensated VGA in 65-nm CMOS

This paper reports a 60-GHz four-element beam-tapering phased-array transmitter with a lower sidelobe level (SLL). The array factor and the error vector magnitude (EVM) were calculated to explain the low sidelobe characteristic of a nonuniform amplitude array and to emphasize the importance of phase compensation, respectively. The phase-compensated radio frequency (RF) variable gain amplifiers (VGAs) were proposed to compensate the gain variance of phase shifters and, simultaneously, excite the nonuniform amplitude to each array element. The proposed VGA improves the relative phase error by 2° and the OP1dB by 2.4 dB within a gain control range of 5 dB, compared to the current steering without any compensation. Implemented in a commercial 65-nm CMOS process, the integrated array chip displays an root-mean-square (rms) gain error of <;0.53 dB and an rms phase error of <;8.8° in the frequency range of 57-66 GHz, while consuming a dc power of 403.2 mW and occupying a chip area of 2.88 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The fabricated array was integrated with a 1 × 4 Teflon array antenna to verify the beamforming and beam-tapering operations. With proper gain and phase control, the integrated array decreases the SLL by up to 5.2 dB, and the minimum SLL is -15.2 dB. To the best of the authors' knowledge, this is the first report on the implementation of CMOS beamtapering arrays in the 60-GHz band.