RMS Amplitude Error Research Articles

Design and Performance of a Wideband Ka-Band 5-b MMIC Phase Shifter

In this letter, the design and performance of a Ka-band 5-b monolithic microwave integrated circuit phase shifter is presented. In the 180° phase bit, a developed switched-path-type topology is employed in order to extend the bandwidth and achieve good phase shifting characteristics. The fabricated phase shifter demonstrates an rms phase error of less than 4.7° and an rms amplitude error of less than 0.6 dB over the frequency band from 31 to 40 GHz. The input and output return loss is measured to be better than 9 dB, and the chip size is 2.55 mm $\times1.3$ mm.

UAV 공중 네트워크를 위한 손실 없는 Polyphase I/Q 네트워크 및 능동 벡터 변조기 기반 빔-포밍 수신기

본 논문은 무인기(UAV) 기반 공중 네트워크 시스템을 위한 polyphase In-phase/Quadrature-phase(I/Q) 네트워크 기반 빔-포밍 수신부를 제안한다. 제안하는 polyphase I/Q 네트워크는 낮은 Q-factor와 높은 임피던스를 갖기 때문에 작은 손실로 벡터 변조기를 구동할 수 있다. 벡터 변조기는 가변 이득 증폭기(VGA)로 구성되며, In-phase 및 Quadrature-phase 위상 신호의 진폭 제어 및 벡터 합을 통해 위상을 가변한다. 제안하는 빔-포밍 수신부는 TSMC <TEX>$0.18{\mu}m$</TEX> CMOS 공정을 통해 구현하였다. 프로토타입은 5-6GHz 주파수 대역(-40dB 입력)에서 검증하였다. 6bit 벡터 변조기 제어를 통해 <TEX>$5.6^{\circ}$</TEX> LSB (least significant bit)로 <TEX>$360^{\circ}$</TEX> 위상 가변이 가능하다. 위상 오차는 평균 <TEX>$1.6^{\circ}$</TEX>이며, 진폭 오차는 평균 0.3dB이다. This paper presents a beam-forming receiver with polyphase In-phase/Quadrature-phase (I/Q) network for airborne communication. In beam-forming receiver, the insertion loss (IL) difference between input path increases the receiver noise figure (NF). The major element for generating IL difference is the impedance variation of phase shifter. In order to maintain a constant IL in every phase, this paper propose a lossless polyphase I/Q network based beam-forming receiver. The proposed lossless polyphase I/Q network has low Q-factor and high impedance for drive back-end VGA (Variable gain amplifier) block with low insertion loss. The 2-stage VGA controls in-phase and quadrature-phase amplitude level for vector summation. The proposed beam-forming receiver prototype is fabricated in TSMC <TEX>$0.18{\mu}m$</TEX> CMOS process. The prototype cover the <TEX>$360^{\circ}$</TEX> with <TEX>$5.6^{\circ}$</TEX> LSB. The average RMS phase error and amplitude error is approximately <TEX>$1.6^{\circ}$</TEX> and 0.3dB.

X-Band 6-Bit Phase Shifter with Low RMS Phase and Amplitude Errors in 0.13-㎛ CMOS Technology

This paper proposes a CMOS 6-bit phase shifter with low RMS phase and amplitude errors for an X-band phased array antenna. The phase shifter combines a switched-path topology for coarse phase states and a switch-filter topology for fine phase states. The coarse phase shifter is composed of phase shifting elements, single-pole double-throw (SPDT), and double-pole double-throw (DPDT) switches. The fine phase shifter uses a switched LC filter. The phase coverage is 354.35° with an LSB of 5.625°. The RMS phase error is ＜ 6° and the RMS amplitude error is ＜ 0.45 ㏈ at 8–12 GHz. The measured insertion loss is ＜ 15 ㏈, and the return losses for input and output are ＞ 13 ㏈ at 8–12 ㎓. The input P1dB of the phase shifter achieves > 11 ㏈m at 8–12 ㎓. The current consumption is zero with a 1.2-V supply voltage. The chip size is 1.46´0.83 ㎟, including pads.

A Novel Concurrent 22–29/57–64-GHz Dual-Band CMOS Step Attenuator With Low Phase Variations

A novel 22–29/57–64-GHz concurrent dual-band CMOS 4-bit step attenuator with small phase variations is presented. A new integrated diplexer-attenuator possessing both attenuation and diplexer filtering functions is used to achieve the concurrent dual-band response for the 22–29/57–64-GHz concurrent dual-band attenuator, which leads to small size and low insertion loss. The 22–29/57–64-GHz concurrent dual-band attenuator also includes a new distributed attenuator configured to result in small phase variation. The 22–29/57–64-GHz concurrent dual-band attenuator is fabricated using a 0.18- $\mu {\text {m}}$ BiCMOS technology. The measured insertion loss, root-mean-square (rms) amplitude error, and rms phase error are less than 7.9 dB, 0.55 dB, and 4.7° in the first passband of 22–29 GHz, respectively. In the second passband, 57–64 GHz, the measured insertion loss, rms amplitude error, and rms phase error are less than 11 dB, 1.5 dB, and 4.1°, respectively. The measured stopband rejections over the 16 states are greater than 28 and 31 dB at 12 and 36 GHz, respectively. The core chip size is $1.8\,\times \, 0.52~{\text {mm}}^{2}$ .

A Highly Integrated 1-Bit Phase Shifter Based on High-Pass/Low-Pass Structure

This letter presents a highly integrated 1-bit 90 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> phase shifter based on high-pass/low-pass structure for 60 GHz beamforming applications using a standard 65 nm CMOS process. In order to overcome the limitation of the conventional low-pass only phase shifter, the combination of high-pass/low-pass network was utilized as a 1-bit phase shifter. By integrating a high pass network into the low-pass network with low loss single-pole single throw (SPST) switches that adapt a resistive body floating technique, the proposed phase shifter achieves average 5 dB IL and less than ±0.18 dB of insertion loss flatness and 1 dB rms amplitude error over the whole band in a small chip area of 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including pads.

A 44 GHz CMOS RFIC Dual-Function Attenuator with Band-Pass-Filter Response

A dual-function attenuator possessing both attenuation and band-pass filtering functions is proposed. The new dual-function band-pass attenuator architecture is derived by replacing the quarter-wavelength transmission line of a conventional attenuator with a 2nd-order admittance-inverter band-pass filter. Design formulas for the dual-function band-pass attenuator are derived. A 3-b CMOS dual-function band-pass step attenuator designed using a 0.18 $\mu{\rm m}$ BiCMOS technology shows measured insertion loss of 4.4–5.9 dB, RMS amplitude error of 0.8–1.4 dB, RMS phase error of 1.9–6.7 $^{\circ}$ over 36–52 GHz, input P1dB higher than 20 dBm at 44 GHz, and band-pass-filtering response with stop-band rejections greater than 18 dB at 24 and 64 GHz.

A Ku‐band 3‐bit phase shifter MMIC using GaAs phemt technology for phased array system

ABSTRACTA Ku‐band 3‐bit switch‐type phase shifter with low insertion loss, low magnitude variation, and low rms phase error is designed and fabricated on 0.15‐μm pHEMT process. For all eight states, the insertion loss is 6.5 ± 1.5 dB from 10–14 GHz and the input return loss is &gt;8.5 dB over 10–14 GHz. The phase shifter achieves a rms phase error of 2.2° and a rms amplitude error of 0.37 dB at 12 GHz with total chip size of 1.5 ×1 mm2. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:771–774, 2015

A 5-20 GHz 5-Bit True Time Delay Circuit in 0.18 ㎛ CMOS Technology

This paper presents a 5-bit true time delay circuit using a standard 0.18 ㎛ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 ㎓. The RMS group delay and amplitude errors are ＜ 1 ps and ＜2 ㏈, respectively. The measured insertion loss is ＜27 ㏈ and the input and output return losses are ＜12 ㏈ at 5-15 ㎓. The current consumption is nearly zero with 1.8 V supply. The chip size is 1.04 × 0.85 ㎟ including pads.

Broadband compact InGaAs pin 5-bit digital attenuator using π-type resistive network

A broadband compact InGaAs pin 5-bit digital attenuator using a π-type resistive network is demonstrated. The proposed 5-bit digital attenuator is composed of π-type resistive networks for good input/output matching and accurate attenuation characteristics. The fabricated attenuator MMIC has good performance characteristics, such as an insertion loss less than 11.5 dB and a small RMS amplitude error of 2.3 dB at the broadband frequency range of 7–40 GHz. In addition, the overall chip size, which is significantly reduced by using the developed multilayer structure, is only 1.59×0.84 mm2.

A High-Linearity $X$-Band Four-Element Phased-Array Receiver: CMOS Chip and Packaging

This paper presents the design and chip-on-board packaging of a high-linearity four-element phased-array receiver for 9-10-GHz applications. The phased-array is built using 0.13-μm CMOS with a single-ended design, and it results in a measured gain of 10.1 dB, an input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of - 12.5dBm, an input IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of -4 dBm, and a noise figure of 3.4 dB at 9.5 GHz. An rms gain error of <;0.4 dB and phase error of <;8° are obtained at 9-10 GHz using an integrated variable gain amplifier and an 11° phase trim bit. The chip occupies an area of 2.5 × 2.9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a power consumption of 36 mW per channel from a 1.8-V supply (144-mW total). The phased array is packaged using chip-on-board techniques and the channel-to-channel coupling is determined either by the chip-to-ground inductance or by coupling between the input bond-wires. Measurements and simulations on channel 1 show that, with well isolated input bond-wires, one can obtain <; -31-dB coupling between the channels, and an rms amplitude and phase error of ~0.2 dB and ~1°, respectively, at 9.5 GHz, when the phase of channels 2-4 are changed. To our knowledge, this is the first in-depth study of coupling in a phased-array chip with packaging considerations.

6-bit CMOS Digital Attenuators With Low Phase Variations for $X$-Band Phased-Array Systems

This paper presents 6-bit CMOS digital step attenuators with low phase variations. To mitigate the insertion phase variation of conventional switched Pi/T attenuators, the proposed attenuators employ a compensation circuit. This includes a low-pass filter for phase/amplitude correction. Analysis and comparison of two types of Pi-attenuators with the inductive and capacitive correction circuits are described. The two types of attenuators are fabricated using a 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox{m}}$</tex> </formula> CMOS process. The attenuators have a maximum attenuation range of 31.5 dB with 0.5-dB steps (64 states). The attenuators with the inductive and capacitive correction structures, respectively, exhibit root mean square (rms) amplitude errors of less than 0.3 and 0.4 dB, and rms phase errors of less than 3.5 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex> </formula> and 2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex> </formula> at 8–12 GHz. The insertion losses are 8.7 and 10.5 dB at 10 GHz, respectively. The input 1-dB compression points are 15 and 13 dBm at 10 GHz, and the total chip sizes, excluding pads, are <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${\hbox{1.25}}\times {\hbox{0.4}}~{\hbox{mm}}^{2}$</tex> </formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox{0.67}}\times {\hbox{0.5}}~{\hbox{mm}}^{2}$</tex></formula> .

A Bidirectional TX/RX Four-Element Phased Array at 60 GHz With RF-IF Conversion Block in 90-nm CMOS Process

A 60-GHz four-element bidirectional phased-array transmitter/receiver (TX/RX) chip with a two bit phase shifter (PS) and IF converter to/from 12 GHz, using a 90-nm CMOS process, is described. The array features 7-dB gain, measured noise figure of 9 dB, IPldB of -19 dBm for RX, and output Psat of +3.5 dBm for TX, drawing 60 mA from a 1.3-V supply. The rms amplitude and phase error of the PS is 0.7 dB and 2° max, respectively, from 57 to 66 GHz. This new architecture, together with the compact layout, decreases chip size by a factor of 2, compared to a separate TX and RX design. The use of passive PSs and combiners reduces the current consumption and minimizes temperature variation. An additional rms error of 0.3° and 0.07 dB was measured from 0°C to 80°C. Total die area is 1.6 × 1 mm2 and 1.6 × 0.65 mm2 with and without an IF converter block, respectively. First pass success was achieved by the closed ground environment design methodology of the passive structures and by proper layout. To our knowledge, this is the first report on a bidirectional 60-GHz array with the lowest reported chip power consumption and size.

A Ka-band 3-bit RF MEMS true-time-delay network

A monolithic Ka-band true-time-delay (TTD) switched-line network containing 12 metal-to-metal contact RF microelectromechanical system switches has been successfully fabricated and characterized on a 75-/spl mu/m-thick GaAs substrate. The compact 9.1-mm/sup 2/ TTD network was designed to produce flat delay time over a dc-to-40-GHz bandwidth with full 360/spl deg/ phase control at 45/spl deg/ intervals at 35 GHz. Measurements show a match to within 2% to the designed delay times at 35 GHz for all eight switch states with 2.2-dB average insertion loss over all states. Peak rms phase error is 2.28/spl deg/ and peak rms amplitude error is 0.28 dB from dc to 40 GHz. Return loss better than 15 dB from dc to 40 GHz for all eight states confirms the circuit's broad-band operation.

Effect of element failure and random errors in amplitude and phase on the sidelobe level attainable with a linear array

In experiments with linear arrays at sea, one frequently operates with an array which has not only errors in amplitude and phase between channels but also inoperative elements. Previous calculations have shown that in the presence of random errors in amplitude and phase, the sidelobe level of the mean beam pattern is the sum of that of the error-free pattern plus an angle-independent background level due to the random errors. If the time constant of the random process is much larger than the integration time of the beamformer (as is most often the case), then a more relevant statistic is the mean value of the peak sidelobe due to a single realization of the random process. Our numerical calculations show that this value can be substantially larger (approximately 6 dB) than the peak sidelobe of the mean beam pattern. When the error-related sidelobes are predominant, appreciably greater sidelobe suppression cannot be achieved by using a set of amplitude weights which yield an error-free sidelobe level less than that of the error-related level. Element failure also produces an elevated sidelobe level whose peak value can be estimated and in many cases bounded above by the ratio of the sum of the amplitude weights of the faulty elements to the sum of the amplitude weights of the functioning elements. This ratio is nearly linearly related to the rms amplitude and phase errors in the way in which each affects the peak sidelobe level. This allows one to construct a characteristic curve for the peak sidelobe level in the presence of all these degrading factors, given an array of N elements and a set of amplitude weights. Processing techniques are available which may allow one to regain the sidelobe suppression lost due to inoperative elements. Among such techniques are algorithms for adjusting the amplitude weights, cross-sensor beamforming, subaperture processing and a procedure for estimating the signal at inoperative elements by using those from neighboring elements.

Statistical patterns of a general array

The present analysis considers the effects of Gaussian errors upon the antenna pattern of any array of elements. Analytical solutions for an average pattern and the standard deviation about this average are found. The errors are described in terms of the rms amplitude and phase errors at each element, with a correlation function relating errors in neighboring elements. The results are applied to the case of an array consisting of a sector of a circular array, with the resulting statistical patterns plotted. Then the problem of assigning probabilities to statements about the actual antenna pattern, based upon the statistical plots, is discussed.