Rm GS Research Articles

Corrigendum to “On the conjecture of Ulam on the invariance of measure in the Hilbert cube” (Colloq. Math. 152 (2018), 79–95)

In this corrigendum, we mainly revise Lemma 5.1 of the paper by introducing an extension $F : {\rm GS}(J,p) \to M_a$ of the surjective $d_a$-isometry $f : J \to K$, where $J$ is an infinite-dimensional interval defined as $ J = \prod _{i=1}^\infty J_i $ w

Stochastic Resonance in Bioinspired Electronic Device Using Polymer Field Effect Transistors

Stochastic resonance (SR) phenomenon is emerged in organic field effect transistors (OFETs) using $\pi$-conjugated polymer, where application of external noise to the OFET system enhances signal/information processing performance which is often found in biological systems.The channel conductivity of the OFET is slightly increased by spin-coating using heated semiconductor polymer solution with heated glass substrate.In order to improve frequency responses of OFET, optimal width of the gate electrode is explored. Furthermore, it turns out that scratching and removing semiconductor film outside the source-drain electrodes and the channel enhances the On-Off current ratio of the device. These fabrication processes lead to steeper nonlinearity on the $I_{\rm DS}$ {\it vs.} $V_{\rm GS}$ curve, resulting in emergence of SR, which is fingerprinted in increase of correlation value between input and output signals with increase of intensity of external noise.

Astrophysical S factor of the N14(p,γ)O15 reaction at 0.4–1.3 MeV

The $^{14}\textrm{N(p,}\gamma\textrm{)}^{15}\textrm{O}$ reaction is the slowest reaction of the carbon-nitrogen cycle of hydrogen burning and thus determines its rate. The precise knowledge of its rate is required to correctly model hydrogen burning in asymptotic giant branch stars. In addition, it is a necessary ingredient for a possible solution of the solar abundance problem by using the solar $^{13}$N and $^{15}$O neutrino fluxes as probes of the carbon and nitrogen abundances in the solar core. After the downward revision of its cross section due to a much lower contribution by one particular transition, capture to the ground state in $^{15}$O, the evaluated total uncertainty is still 8\%, in part due to an unsatisfactory knowledge of the excitation function over a wide energy range. The present work reports precise S-factor data at twelve energies between 0.357-1.292~MeV for the strongest transition, capture to the 6.79~MeV excited state in $^{15}$O, and at ten energies between 0.479-1.202~MeV for the second strongest transition, capture to the ground state in $^{15}$O. An R-matrix fit is performed to estimate the impact of the new data on astrophysical energies. The recently suggested slight enhancement of the 6.79~MeV transition at low energy could not be confirmed. The present extrapolated zero-energy S-factors are $S_{6.79}(0)$~=~1.24$\pm$0.11~keV~barn and $S_{\rm GS}(0)$~=~0.19$\pm$0.05~keV~barn.

Failure Analysis of 1200-V/150-A SiC <sc>MOSFET</sc> Under Repetitive Pulsed Overcurrent Conditions

SiC MOSFETs are a leading option for increasing the power density of power electronics; however, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics have to be further understood. Two SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/150 A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress. This research supplements recent work that demonstrated the long term reliability of these same devices [1] . Using an RLC pulse-ring-down test bed, these devices hard-switched 600 A peak current pulses, corresponding to a current density of 1500 A/cm2. Throughout testing, static characteristics of the devices such as $B_{{\rm VDSS}}$ , $R_{{\rm DS}({\rm on})}$ , and $V_{{\rm GS}({\rm th})}$ were measured with a high power device analyzer. The experimental results indicated that a conductive path was formed through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO2 interface as a result of the extreme high current density present in the device's JFET region. However, the high peak currents and repetition rates required to produce the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs under the pulsed overcurrent conditions common in power electronic applications.

Influence of the Gate Height Engineering on the Intrinsic Parameters of UDG-MOSFETs With Nonquasi Static Effect

This paper presents the results of a systematic theoretical investigation on the impact of gate height on the analog and radio-frequency (RF) performances of underlap-FinFET devices. The conventional underlap-FinFETs offer lower on current $(I_{\rm on} )$ and higher distributed channel resistance $(R_{\rm ch} )$ . This paper shows that a higher gate height improves both $I_{\rm on} $ and $R_{\rm ch} $ due to higher gate side-wall fringing fields. In this paper, the various figure of merits (FOMs) for analog applications of the underlap-FinFETs such as drain current $(I_{\rm ds} )$ , transconductance $(g_{m} )$ , transconductance generation factor $(g_{m} /I_{\rm ds} )$ , output resistance $(R_{o} )$ , and intrinsic gain $(g_{m} R_{o} )$ are systematically analyzed for different values of gate height and reported. The RF FOMs studied include intrinsic capacitances $(C_{\rm gs} , C_{\rm gd} )$ and resistances $(R_{\rm gs} , R_{\rm gd} )$ , transport delay $(\tau _{m} )$ , cutoff frequency $(\,f_{T} )$ , and the transit frequency of maximum available power gain $(\,f_{\rm MAX} )$ . This paper clearly demonstrates that the gate height is a critical technology parameter in improving the analog performance of underlap-FinFETs.

Junctionless Gate-All-Around pFETs Using <italic>In-situ</italic> Boron-Doped Ge Channel on Si

Junctionless devices exhibit favorable $I_{{\rm on}}/I_{{\rm off}}$ and SS in high-mobility Ge channels owing to the elimination of junction leakage. With channel doping of 5 × 1018 cm−3, the fin width of 27 nm and the gate length of 250 nm, our gate-all-around device has the $I_{{\rm on}}/I_{{\rm off}}$ of 1 × 106, the SS of 95 mV/dec, and the $I_{{\rm on}}$ of 275 μA/μm. The drain current reaches 390 μA/μm for the device with channel doping of 8 × 1019 cm−3, and the fin width of 9 nm. The junctionless devices show higher mobility in the large $V_{{\rm GS}} -V_{T}$ region than the inversion mode devices due to less dependence on surface roughness scattering. Junctionless devices also show increasing drive current at increasing temperatures due to the nature of impurity scattering.

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Guided by the Wentzel-Kramers–Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ${I} _{\rm D} = 64~\mu $ A/ $\mu $ m at ${V} _{\rm DS} = {V} _{\rm GS} - {V} _{\rm off} = -1.0$ V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at ${V} _{\rm DD}$ as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm2 at $V_{{\rm GS}} = V_{{\rm DS}} = 0.4$ V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K.

A Simple Method to Estimate the Output Power and Efficiency Load–Pull Contours of Class-B Power Amplifiers

This paper describes a simple method to estimate the output power and efficiency load–pull contours of a class-B power amplifier (PA). Using successively improved–but still simple and intuitive—field-effect transistor nonlinear ${i}_{\rm DS}({v}_{\rm GS},{v}_{\rm DS})$ current models, this work starts by explaining the poor efficiency predictions provided by the Cripps load-line method, to then derive refined expressions to predict the output power load–pull contours and a novel analysis that produces useful estimates of the efficiency load–pull contours. These estimates are believed to constitute an invaluable tool for the analysis and design of single-ended class-B or Doherty PAs.

Dual-Sweep Combinational Transconductance Technique for Separate Extraction of Parasitic Resistances in Amorphous Thin-Film Transistors

We report a dual-sweep combinational transconductance technique for separate extraction of parasitic source (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> ) and drain (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) resistances in thin-film transistors (TFTs) by combining forward and reverse transfer characteristics. In the proposed technique, gate bias-dependent total resistance [R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TOT</sub> (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> )] and degradation of the transconductance due to the parasitic resistance at the source terminal during the dual-sweep characterization are employed. Applying the proposed technique to amorphous oxide semiconductor TFTs with various combinations of channel length (L) and width (W), we successfully separated R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> . A model for the W- and L-dependences of the extracted parasitic resistances is also provided.

A Double-gate Power LDMOS with Improved SOA by Complementary Majority Carrier Conduction Paths

An $\bm{n}$ -type power LDMOS with an integrated $\bm{p}$ -MOS is proposed to improve the safe operation area. The proposed structure has three external terminals and majority carriers of both types are used for conduction under high-voltage and high-current condition. The $\bm{p}$ -MOS is implemented outside of the voltage-sustaining region of the $\bm{n}$ -MOS. Under high-voltage and high-current condition, the gate of the $\bm{p}$ -MOS is turned ON by a self-generated negative gate-to-source voltage. Majority hole current from $\bm{p}$ -MOS is introduced into the $\bm{p}$ -top region. It alters the electric field profile in the voltage-sustaining region and reduces impact ionization. As a result, the output I – V curves become flatter and the saturation current is more than twice of that of a conventional $\bm{n}$ -MOS with the same breakdown voltage at $V_{{\rm GS}} \geq 8 {\rm V}$ .

Intrinsic Channel Mobility of Amorphous, In–Ga–Zn–O Thin-Film Transistors by a Gated Four-Probe Method

Intrinsic mobility and intrinsic channel resistance $(R_{\rm CH})$ of amorphous, In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs) with varying channel length $(L)$ are investigated using a gated four-probe back-channel-etched TFT design. The intrinsic $R_{\rm CH}$ is found to decrease from ${\sim}{500}$ to ${\sim}{\rm 250}~{\rm k}\Omega$ per unit area by increasing $V_{\rm GS}$ from 10 to 20 V. The intrinsic mobility is ${\sim}{\rm 17}~{\rm cm}^{2}/{\rm V}\cdot{\rm s}$ , which is about 20% higher than that derived from the normal two-point probe measurements. Source and drain parasitic resistance $(R_{\rm PAR})$ of the a-IGZO TFTs is found to be of the same order of magnitude as the $R_{\rm CH}$ —which is different from hydrogenated amorphous-silicon (a-Si:H) TFTs, where TFT operation is dominated by $R_{\rm PAR}$ .

Unified Subthreshold Coupling Factor Technique for Surface Potential and Subgap Density-of-States in Amorphous Thin Film Transistors

We report a unified subthreshold coupling factor technique for a simultaneous extraction of the surface potential $(\psi_{\rm S})$ and the subgap density-of-states [DOS: $g(E)$ ] over the bandgap in amorphous semiconductor thin film transistors (TFTs). It is fully based on the experimental gate bias-dependent coupling factor $[m(V_{\rm GS})]$ under subthreshold bias. Through the proposed technique only with current-voltage data under subthreshold operation, a unified extraction of the DOS with a consistent mapping of the gate bias $(V_{\rm GS})$ to the subgap energy is obtained. Applying to amorphous InGaZnO TFTs, $g(E)$ is obtained to be a superposition of two exponential functions with $N_{\rm TA}=1.62\times 10^{17}~{\rm eV}^{-1}~{\rm cm}^{-3}$ and $kT_{\rm TA}=0.026~{\rm eV}$ for the tail states while $N_{\rm DA}=6.5\times 10^{16}~{\rm eV}^{-1}~{\rm cm}^{-3}$ and $kT_{\rm DA}=0.22~{\rm eV}$ for the deep states.

Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices

This paper introduces a high-density layout style named overlapping circular-gate transistor (O-CGT) that allows the overlapping of circular gates from neighboring cells. With reference to rectangular-gate transistors (RGTs), higher aspect ratio per active area can be achieved. Besides, stray junction capacitances are minimal, improving switching performance. The first-order model for the O-CGT aspect ratio is used to size high-current devices of nominal on-resistance/current rate of 3.3 Ω/10 mA and 20 mΩ/2 A at V <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$_{\rm GS}$</tex></formula> = 4.5 V. These power transistors were prototyped according to a standard mixed-signal 0.35-μm CMOS process and, respectively, occupy 1410 μm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^2$</tex></formula> and 0.541 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^2$</tex> </formula> , which represent an area saving of up to 60% as compared to RGTs of equivalent aspect ratio. Excellent fitting between O-CGT analytical and experimental data is attained. O-CGTs and RGTs exhibit very close I <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$_{\rm DS}$</tex></formula> × V <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$_{\rm GS}$</tex></formula> characteristics, with deviations limited to 0.8% and 5.36% on subthreshold and strong inversion regions, respectively. The O-CGT drain-source breakdown voltage is 8.91 V, slightly above RGT. The O-CGT topology represents then a good option in designing power stages in smart-power chips using planar fabrication processes.

In vitro evaluation of the potential for drug-induced toxicity based on 35S-labeled glutathione adduct formation and daily dose

Drug-induced toxicity such as idiosyncratic drug toxicity is believed to be reduced when either reactive metabolite formation or exposure to a drug is minimized. The objective of the present study was therefore to clarify the relationship between the daily doses, the formation rates of reactive metabolite adduct with (35)S-glutathione (RM-GS) and the safety profiles of compounds. The RM-GS formation rates for 113 test compounds were determined by incubation with human liver microsomes, and the test compounds were classified into three categories of safe, warning and withdrawn/black box warning. A total of 23 out of 28 withdrawn/black box warning drugs showed both a RM-GS formation rate of over 1 pmol/30 min/mg protein and a dose of over 100 mg. These results suggest that when compounds are plotted in this region, the compounds would have a relatively high idiosyncratic drug toxicity potential.

High-$V_{\rm GS}$ PFET DC Hot-Carrier Mechanism and Its Relation to AC Degradation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Recently, negative bias temperature instability (NBTI) enhanced by local self-heating has been proposed as a mechanism for high-<formula formulatype="inline"><tex Notation="TeX">$V_{g}$</tex></formula> PFET “hot-carrier” degradation. This is based on the idea that the effective temperature for NBTI is increased in the drain region due to a very localized self-heating effect reported in the literature by Pop and others. Our PFET dc stress data are consistent with local self-heating activated NBTI at high <formula formulatype="inline"><tex Notation="TeX">$V_{g}$</tex></formula> , but at mid <formula formulatype="inline"><tex Notation="TeX">$V_{g}$</tex></formula>, we observed similar behavior to typical NFET hot carriers, i.e., energy-driven hot carrier (EDHC). If self-heating is involved with the PFET high- <formula formulatype="inline"><tex Notation="TeX">$V_{g}$</tex></formula> dc degradation, the question of ac behavior naturally arises. Our PFET ring-oscillator stress results demonstrate that the high-<formula formulatype="inline"><tex Notation="TeX">$V_{\rm GS}$</tex></formula> PFET hot carrier dominant under dc stress does not significantly contribute under typical CMOS switching conditions, whereas the mid-<formula formulatype="inline"><tex Notation="TeX">$V_{\rm GS}$</tex></formula> hot carrier does. This supports the idea that the predominant damage mechanism involved at high <formula formulatype="inline"> <tex Notation="TeX">$V_{\rm GS}$</tex></formula> is NBTI enhanced by local self-heating with a thermal time constant longer than a few hundred picoseconds. </para>

SThM Temperature Mapping and Nonlinear Thermal Resistance Evolution With Bias on AlGaN/GaN HEMT Devices

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Channel temperature has a strong impact on the performance of a microwave power transistor. In particular, it has a strong influence on the power gain, energetic efficiency, and reliability of the device. The thermal optimization of device geometry is therefore a key issue, together with precise measurements of temperature within the channel area. In this paper, we have used scanning thermal microscopy to perform temperature mapping, at variable dc bias points, on an AlGaN/GaN high-electron mobility transistor made on epilayers grown on silicon carbide substrate. We have analyzed the variation of the thermal resistance values, which are deduced from these measurements, with bias conditions <formula formulatype="inline"><tex>$V_{\rm GS}$</tex></formula> and <formula formulatype="inline"><tex>$V_{\rm DS}$</tex></formula>. The observed nonlinear behavior is found to be in excellent agreement with physical simulations, strongly pointing out the large variability of the extension of the dissipation area with the dc bias conditions. </para>

Generalized Steiner Systems {\rm GS}(2, 4, v, 2) with v a Prime Power \equiv 7 ({\it mod}\ {12})

Generalized Steiner systems {\rm GS}(2, 4, v, g) were first introduced by Etzion and were used to construct optimal constant weight codes over an alphabet of size g+1 with minimum Hamming distance 5, in which each codeword has length v and weight 4. Etzion conjectured that the necessary conditions v\equiv 1 ({\it mod}\ {3}) and v \geq 7 are also sufficient for the existence of a {\rm GS}(2,4,v,2). Except for the example of a {\rm GS}(2,4,10,2) and some recursive constructions given by Etzion, nothing else is known about this conjecture. In this paper, Weil's theorem on character sum estimates is used to show that the conjecture is true for any prime power v\equiv 7 ({\it mod}\ {12}) except v=7, for which there does not exist a {\rm GS}(2,4,7,2).

Is Formula an eclipsing black-hole binary?

We present an alternative interpretation of the quiescent optical light curve of |${\rm GS}2000+25$| published by Chevalier & Ilovaisky, and show that the modulation can be explained by a single periodicity. Using a method that is independent of the characteristics of the modulation of the light curve, we obtain an alternative value for the orbital period of 0.2935 d, which is twice the 1-d alias of half Chevalier & Ilovaisky's orbital period. The modulation can either be explained as primarily due to the ellipsoidal variations of the secondary star or as a combination of the above and an eclipse. From X-ray data taken during outburst and decline, we find no evidence of an eclipse of the compact object, and therefore the eclipse required must involve the secondary star and the accretion disc. Assuming an accretion disc comparable to that in |$A0620-00$|⁠, for the eclipsing case we find the system to lie in the inclination range |$62^{\circ}-82^{\circ}$|⁠, and for the ellipsoidal case in the range |$56^{\circ}-79^{\circ}$|⁠.