Rm DS Research Articles

One-Dimensional Edge Contacts to a Monolayer Semiconductor

Integration of electrical contacts into van der Waals (vdW) heterostructures is critical for realizing electronic and optoelectronic functionalities. However, to date no scalable methodology for gaining electrical access to buried monolayer two-dimensional (2D) semiconductors exists. Here we report viable edge contact formation to hexagonal boron nitride (hBN) encapsulated monolayer MoS2. By combining reactive ion etching, in situ Ar+ sputtering and annealing, we achieve a relatively low edge contact resistance, high mobility (up to ∼30 cm2 V-1 s-1) and high on-current density (>50 μA/μm at VDS = 3V), comparable to top contacts. Furthermore, the atomically smooth hBN environment also preserves the intrinsic MoS2 channel quality during fabrication, leading to a steep subthreshold swing of 116 mV/dec with a negligible hysteresis. Hence, edge contacts are highly promising for large-scale practical implementation of encapsulated heterostructure devices, especially those involving air sensitive materials, and can be arbitrarily narrow, which opens the door to further shrinkage of 2D device footprint.

COSS Losses in 600 V GaN Power Semiconductors in Soft-Switched, High- and Very-High-Frequency Power Converters

We report losses from charging and discharging the parasitic output capacitor, ${\rm C}_{\rm OSS}$ , in Gallium Nitride (GaN) power devices with voltage ratings over 600 ${\rm V}_{\rm DS}$ . These losses are of particular importance in soft-switched circuits used at MHz switching frequencies, where the output capacitance of the device is charged and discharged once per switching cycle during the device's off-time. This process is assumed lossless. We measure ${\rm C}_{\rm OSS}$ losses from 5–35 MHz sine, square, and Class- $\Phi _{2}$ waveshapes in enhancement-mode and cascode devices, and find that losses are present in all tested devices, equal or greater than conduction losses at MHz frequencies, and exponentially increasing with $\mathbf{dV/dt}$ . The cascode device outperforms the e-mode devices under 300 V, but the e-mode devices are preferred above this operating voltage. Furthermore, we show that, within a device family, losses scale linearly with output energy storage. Packaging appears to have only a minor effect on these losses. Finally, we demonstrate 10 MHz, 200 W dc–dc converters with varying device configurations, showing that, even with constant circulating currents, moving to larger devices with lower ${\rm R}_{\rm DS,ON}$ actually degrades efficiency in certain applications due to ${\rm C}_{\rm OSS}$ losses. In the high-voltage, high-frequency range, these reported losses must be optimized simultaneously with conduction losses on a per-application basis.

Stochastic Resonance in Bioinspired Electronic Device Using Polymer Field Effect Transistors

Stochastic resonance (SR) phenomenon is emerged in organic field effect transistors (OFETs) using $\pi$-conjugated polymer, where application of external noise to the OFET system enhances signal/information processing performance which is often found in biological systems.The channel conductivity of the OFET is slightly increased by spin-coating using heated semiconductor polymer solution with heated glass substrate.In order to improve frequency responses of OFET, optimal width of the gate electrode is explored. Furthermore, it turns out that scratching and removing semiconductor film outside the source-drain electrodes and the channel enhances the On-Off current ratio of the device. These fabrication processes lead to steeper nonlinearity on the $I_{\rm DS}$ {\it vs.} $V_{\rm GS}$ curve, resulting in emergence of SR, which is fingerprinted in increase of correlation value between input and output signals with increase of intensity of external noise.

De Sitter thin brane model

We discuss the large mass hierarchy problem in a braneworld model which represents our acceleratively expanding universe. The Randall-Sundrum (RS) model with warped one extra dimension added to flat 4-dimensional space-time cannot describe our expanding universe. Here, we study instead the de Sitter thin brane model. This is described by the same action as that for the RS model, but the 4-dimensional space-time on the branes is $\rm dS_4$. We study the model for both the cases of positive 5-dimensional cosmological constant $\Lambda_5$ and negative one. In the positive $\Lambda_5$ case, the 4-dimensional large hierarchy necessitates a 5-dimensional large hierarchy, and we cannot get a natural explanation. On the other hand, in the negative $\Lambda_5$ case, the large hierarchy is naturally realized in the 5-dimensional theory in the same manner as in the RS model. Moreover, another large hierarchy between the Hubble parameter and the Planck scale is realized by the ${\mathcal O}(10^2)$ hierarchy of the 5-dimensional quantities. Finally, we find that the lightest mass of the massive Kaluza-Klein modes and the intervals of the mass spectrum are of order $10^2\,\rm GeV$, which are the same as in the RS case and do not depend on the value of the Hubble parameter.

Three-Level PWM Floating H-Bridge Sinewave Power Inverter for High-Voltage and High-Efficiency Applications

This paper presents a topology of a single-phase floating full-bridge three-level pulse width modulation (PWM) power inverter suitable for high-voltage/high-power dc–ac conversion. High power efficiency is obtained thanks to the slow (50/60 Hz) biasing of the H-bridge power supply terminals, allowed by a particular arrangement and control of two complementary active neutral point clamped voltage-source converters. As result, the main PWM switching voltage as well as the maximum drain–source voltage $V_{{\rm DSS}}$ of related transistors are reduced to one-half of the input $V_{DD}$ voltage. This is allowed by the internally generated and accurately balanced middle-node voltage $V_{DD}/2$ . Consequently, advantageous $r_{{\rm DS}({\rm on})}$ of the low-voltage transistors, along with reduced switching PWM voltage result in considerable decreasing of power losses in whole output power range. This paper introduces the main concept of the floating H-bridge topology, and presents in detail the circuit realization. The performances are demonstrated on $450 V_{{\rm DC}}/230 V_{{\rm AC}}$ 2 kW power inverter exhibiting 98.6% peak efficiency and realized in very small $100\times 60\times 30$ mm3 volume.

A Single-Switch Converter With High Step-Up Gain and Low Diode Voltage Stress Suitable for Green Power-Source Conversion

This paper proposes a single-switch converter with high step-up gain and low diode voltage stress, suitable for green power source conversion. By employing a coupled inductor and switched capacitor, the proposed converters achieve high step-up conversion ratio without adopting extremely high duty ratio or high turns ratio. The voltage spike that occurs on the power switch is alleviated, which allows a low-voltage-rated power switch with low $R_{\rm DS(\mathrm{\scriptscriptstyle ON})}$ to be adopted, thus reducing the conduction losses. Because the energy of the leakage inductor is recycled, the efficiency is improved. In addition, all diodes’ voltage stresses are lowered and are the same, so the selection of power diodes is convenient. Finally, a 300-W prototype circuit with an input voltage of 24 V and an output voltage of 400 V is implemented to verify the performance and functionality of the presented converter. Moreover, the measured highest efficiency is 95.4%.

Failure Analysis of 1200-V/150-A SiC <sc>MOSFET</sc> Under Repetitive Pulsed Overcurrent Conditions

SiC MOSFETs are a leading option for increasing the power density of power electronics; however, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics have to be further understood. Two SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/150 A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress. This research supplements recent work that demonstrated the long term reliability of these same devices [1] . Using an RLC pulse-ring-down test bed, these devices hard-switched 600 A peak current pulses, corresponding to a current density of 1500 A/cm2. Throughout testing, static characteristics of the devices such as $B_{{\rm VDSS}}$ , $R_{{\rm DS}({\rm on})}$ , and $V_{{\rm GS}({\rm th})}$ were measured with a high power device analyzer. The experimental results indicated that a conductive path was formed through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO2 interface as a result of the extreme high current density present in the device's JFET region. However, the high peak currents and repetition rates required to produce the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs under the pulsed overcurrent conditions common in power electronic applications.

A 10-MHz Isolated Synchronous Class-Φ2 Resonant Converter

Because of the forward recovery, the performance of the diodes degrades seriously at multimegahertz, causing extremely high power loss. So, the synchronous rectification (SR) is strongly desired in the multimegahertz resonant converters. This paper proposes a self-driven level-shifted resonant gate driver (RGD) for the SR FET in a 10-MHz isolated class-Φ2 resonant converter. The proposed RGD provides precise switching timing for the SR so that the body diode conduction loss can be minimized. A control stage is introduced to the proposed RGD to block the circulating current and the low-impedance path in the driver to realize ON–OFF control of the converter with high efficiency. The proposed RGD also generates a tunable dc bias to increase the peak gate voltage and extend the conduction time with the optimal $R_{{\rm DS}({\rm on})}$ so that the average $R_{{\rm DS}({\rm on})}$ and the associated conduction loss can be reduced significantly. A 10-MHz prototype with 18-V input and 5-V/2-A output was built. At full load of 2 A, the proposed RGD improves the efficiency from 80.2% using the conventional RGD to 82% (an improvement of 1.8%). Compared to the efficiency of 77.3% using the diode rectification, the efficiency improvement is 4.7% at full load.

A Novel High Step-up DC/DC Converter Based on Integrating Coupled Inductor and Switched-Capacitor Techniques for Renewable Energy Applications

In this paper, a novel high step-up dc/dc converter is presented for renewable energy applications. The suggested structure consists of a coupled inductor and two voltage multiplier cells, in order to obtain high step-up voltage gain. In addition, two capacitors are charged during the switch-off period, using the energy stored in the coupled inductor which increases the voltage transfer gain. The energy stored in the leakage inductance is recycled with the use of a passive clamp circuit. The voltage stress on the main power switch is also reduced in the proposed topology. Therefore, a main power switch with low resistance $R_{{\rm DS} ({\rm ON})}$ can be used to reduce the conduction losses. The operation principle and the steady-state analyses are discussed thoroughly. To verify the performance of the presented converter, a 300-W laboratory prototype circuit is implemented. The results validate the theoretical analyses and the practicability of the presented high step-up converter.

101-GHz InAlN/GaN HEMTs on Silicon With High Johnson’s Figure-of-Merit

In this brief, the InAlN/GaN high-electron mobility transistors (HEMTs) on silicon substrate with high Johnson’s figure-of-merit (J-FOM) are presented. A trilayer photoresist of polymethylmethacrylate (PMMA)/copolymer/PMMA associated with a T-shaped gate is used to reduce the parasitic resistance while maintaining high current gain cutoff frequency. The small dc-to-RF transconductance dispersion of only 1.1% suggests a good quality SiN x passivation layer, and the $f_{\rm MAX}$ of 101 GHz and $f_{T}$ of 60 GHz can be simultaneously obtained with a 0.11- $\mu \text{m}$ foot length and 1.5- $\mu \text{m}$ source-drain distance. In addition, the three-terminal OFF-state breakdown measurements reveal a source-drain breakdown voltage (BV $_{\rm DS})$ of 21 V ( $V_{\rm DG}=31$ V). The results lead to a high J-FOM of 1.3 THz $\,\cdot \,\text{V}$ , which has not been reported for the InAlN/GaN HEMTs on silicon substrate.

Ferroelectricity of HfZrO<sub>2</sub> in Energy Landscape With Surface Potential Gain for Low-Power Steep-Slope Transistors

The corresponding energy landscape and surface potential are deduced from the experimental ferroelectricity of HfZrO2 (HZO) for low-power steep-slope transistor applications. The anti-ferroelectric (AFE) in annealed 600°C HZO extracted electrostatic potential gain from the measured polarization hysteresis loop and calculated subthreshold swing 33 mV/dec over six decades of $I_{\rm DS} $ . A feasible concept of coupling the AFE HZO is experimentally established with the validity of negative capacitance and beneficial for steep-slope FET development in future generation.

Analytical Modeling of Switching Energy of Silicon Carbide Schottky Diodes as Functions of <italic>dI <inline-formula><tex-math notation="LaTeX">$_{\bf DS}$</tex-math></inline-formula>/dt</italic> and Temperature

SiC Schottky Barrier diodes (SiC SBD) are known to oscillate/ring in the output terminal when used as free-wheeling diodes in voltage-source converters. This ringing is due to RLC resonance among the diode capacitance, parasitic resistance, and circuit stray inductance. In this paper, a model has been developed for calculating the switching energy of SiC diodes as a function of the switching rate ( dI $_{\rm DS}/dt$ of the commutating SiC mosfet ) and temperature. It is shown that the damping of the oscillations increases with decreasing temperature and decreasing dI $_{\rm DS}/dt$ . This in turn determines the switching energy of the diode, which initially decreases with decreasing dI $_{\rm DS}/dt$ and subsequently increases with decreasing dI $_{\rm DS}/dt$ thereby indicating an optimal dI $_{\rm DS}/dt$ for minimum switching energy. The total switching energy of the diode can be subdivided into three phases namely the current switching phase, the voltage switching phase, and the ringing phase. Although the switching energy in the current switching phase decreases with increasing switching rate, the switching energy of the voltage and ringing phase increases with the switching rate. The model developed characterizes the dependence of diode's switching energy on temperature and dI $_{\rm DS}/dt$ , hence, can be used to predict the behavior of the SiC SBD.

Fabrication and Characterization of Gate-Last Self-Aligned AlN/GaN MISHEMTs With <italic>In Situ</italic> SiN<sub><italic>x</italic></sub> Gate Dielectric

This paper reports on the fabrication and characterization of gate-last self-aligned <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /AlN/GaN MISHEMTs. The devices featured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> grown SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> by metal–organic chemical vapor deposition as a gate dielectric and for surface passivation. Selective source/drain regrowth was incorporated to reduce contact resistance. SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> sidewall spacers and low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> benzocyclobutene polymer ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa =2.65$ </tex-math></inline-formula> ) supporting layers were employed under the gate head to minimize the parasitic capacitance for high-frequency operation. The device with a gate length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{G})$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.23~\mu \text{m}$ </tex-math></inline-formula> exhibited a maximum drain current density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\rm DS})$ </tex-math></inline-formula> exceeding 1600 mA/mm with a high ON/OFF ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{{\scriptscriptstyle ON}}}/I_{\mathrm{{\scriptscriptstyle OFF}}})$ </tex-math></inline-formula> of over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{7}$ </tex-math></inline-formula> . The current gain cutoff frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{T})$ </tex-math></inline-formula> and maximum oscillation frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\max })$ </tex-math></inline-formula> were 55 and 86 GHz, respectively. In addition, the effect of temperature, from room temperature up to 550 K, on the dc and RF performances of the gate-last self-aligned MISHEMTs was studied.

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Guided by the Wentzel-Kramers–Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ${I} _{\rm D} = 64~\mu $ A/ $\mu $ m at ${V} _{\rm DS} = {V} _{\rm GS} - {V} _{\rm off} = -1.0$ V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at ${V} _{\rm DD}$ as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm2 at $V_{{\rm GS}} = V_{{\rm DS}} = 0.4$ V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K.

A Simple Method to Estimate the Output Power and Efficiency Load–Pull Contours of Class-B Power Amplifiers

This paper describes a simple method to estimate the output power and efficiency load–pull contours of a class-B power amplifier (PA). Using successively improved–but still simple and intuitive—field-effect transistor nonlinear ${i}_{\rm DS}({v}_{\rm GS},{v}_{\rm DS})$ current models, this work starts by explaining the poor efficiency predictions provided by the Cripps load-line method, to then derive refined expressions to predict the output power load–pull contours and a novel analysis that produces useful estimates of the efficiency load–pull contours. These estimates are believed to constitute an invaluable tool for the analysis and design of single-ended class-B or Doherty PAs.

Power Performance at 40 GHz of AlGaN/GaN High-Electron Mobility Transistors Grown by Molecular Beam Epitaxy on Si(111) Substrate

This letter reports on the demonstration of microwave power performance at 40 GHz on AlGaN/GaN high-electron mobility transistor grown on silicon (111) substrate by molecular beam epitaxy. A maximum dc current density of 1.1 $\text{A}\cdot $ mm $^{-1}$ and a peak extrinsic transconductance of 374 mS $\cdot $ mm $^{-1}$ are obtained for 75-nm gate length device. At $V_{\rm DS} = 25$ V, continuous-wave output power density of 2.7 $\text{W}\cdot $ mm $^{-1}$ is achieved at 40 GHz associated with 12.5% power-added efficiency and a linear power gain ( $G_{p})$ of 6.5 dB. The device exhibits an intrinsic current gain cutoff frequency $F_{T}$ of 116 GHz and a maximum oscillation frequency $F_{\rm MAX}$ of 150 GHz. This performance demonstrates the capability of low cost microwave power devices up to Ka-band.

Solution-Processed PbSe Colloidal Quantum Dot-Based Near-Infrared Photodetector

A solution-processed near-infrared (NIR) photodetector based on PbSe colloidal quantum dots (CQDs) with a field-effect transistor (FET) configuration was presented. By blending PbSe CQDs into poly(3-hexylthiophene-2, 5-diyl) (P3HT) as active layer, the photosensitive spectrum of P3HT:PbSe nanocomposites extends into the NIR region. The responsivity and the specific detectivity of FET-based photodetector Au(gate)/PMMA (930nm)/P3HT:PbSe(55nm)/Au(source, drain) reached 500 A/W and $5.02 \times 10^{12}$ Jones, respectively, at $V_{\rm DS}=-40$ V and $V_{\rm G}=-40$ V with 40 mW/cm $^{2}$ of 980-nm laser illumination. It gets more stable due to its reverse fabrication using the dielectric layer to cover the active layer from environment air.

Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips

This brief presents a wide-range temperature sensor with process compensation and nonlinear calibration for HV chip thermal monitoring. Due to a high supply voltage and a large current, HV chips are prone to overheating; thus, they require on-chip temperature sensors to monitor thermal variation. The voltage difference between the drain and source voltages of a metal–oxide–semiconductor, i.e., ${V}_{\rm DS} $ , of HV devices is enlarged by high supply voltages, causing a severe channel length modulation effect to jeopardize the linearity of the saturation current. The proposed calibrated temperature sensors in this brief provide a nonlinear calibration function to resolve this problem. Moreover, our design reveals a process compensation capability by the proposed process variation canceler. The maximal deviation in the range of $(-40 ^{\circ}\hbox{C}, +150) ^{\circ}\hbox{C}$ is measured to be $-2.05 ^{\circ}\hbox{C}$ – $+2.06 ^{\circ}\hbox{C}$ .

One-loop effective action and Schwinger effect in (anti-) de Sitter space

We study the Schwinger mechanism by a uniform electric field in ${\rm dS}_2$ and ${\rm AdS}_2$ and the curvature effect on the Schwinger effect, and further propose a thermal interpretation of the Schwinger formula in terms of the Gibbons-Hawking temperature and the Unruh temperature for an accelerating charge in ${\rm dS}_2$ and an analogous expression in ${\rm AdS}_2$. The exact one-loop effective action is found in the proper-time integral in each space, which is determined by the effective mass, the Maxwell scalar, and the scalar curvature, and whose pole structure gives the imaginary part of the effective action and the exact pair-production rate. The exact pair-production rate is also given the thermal interpretation.