RISC Processor Research Articles

Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware

Abstract—This work studies the impact in the parallel processing of the Interlocked-Hardware-Microkernel (IHM) Plasma microprocessor (IHM-Plasma) by implementing the Earliest-Deadline-First (EDF) algorithm by hardware in the task-scheduler block that belongs to those task-based operational systems, such as that related to the real-time operational systems (RTOS). IHM-Plasma presents Reduced Instruction Set Computer (RISC) architecture. The main results have observed by this study show that the IHM-Plasma running the EDF algorithm by hardware has increased the tasks executed per second in 174% while running a task-based operational system with 14 active tasks in comparison to the original Plasma running the EDF algorithm by software. The developed work has great potential use in Hard Real-Time Systems and others where a rigid control of deadlines is essential and hold many tasks.

Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency

We have demonstrated the execution of several programs stored in an instruction memory by a rapid single-flux-quantum bit-serial 8-bit microprocessor named CORE e2h. We employed a minimal instruction set architecture composed of 13 instructions based on the reduced instruction set computer. We integrated a 128-bit instruction memory and a 128-bit data memory with an arithmetic logic unit, two registers, a program counter, an instruction register, and a controller unit on a single chip. The bit-serial operation was performed by an on-chip clock generator, while the system clocks are provided from room-temperature electronics. The CORE e2h was made up of 11 000 Nb/AlOx/Nb Josephson junctions and fabricated with the Advanced Industrial Science and Technology 10-kA/cm2, 9-Nb-layer process. We obtained the correct results for all the executed programs, including the integer division, the two kinds of summation algorithms, the Euclidean algorithm, and finding the greatest divisor. These test programs contained a single or nested double loop, and the maximum number of executed instructions was 205. We confirmed the stable operation with the DC bias margins of around 10% at 50-GHz for different test programs. The measured electric power consumption was 2.5 mW at 4.2 K, and the estimated computing power was 500 × 106 instructions/s.

Design and Implementation of RISC MIPS Processor on FPGA

Abstract: In this paper, the design and implementation of RISC Processor is proposed with MIPS (Microprocessor without interlocked pipelined stages) technique. This processor performs 16-bit operations using pipelined technique, to improve the performance. This processor performs arithmetic, logical and data movement operations, more efficiently in terms of delay and power. The processor is composed of five stages namely, instruction fetch, instruction decode, execute, memory access and write back. The proposed 16-bit RISC MIPS processor is designed using Verilog and validated using Modelism, it is synthesized using libraries of AMD 45nm technology in Xilinx tool and implemented on Xilinx Spartan 6 FPGA. The proposed RISC MIPS gives reduced overall delay of 3.565ns and overall power consumption of 0.014W.

Comparative Study of RISC AND CISC Architectures

Comparative Study of RISC AND CISC Architectures

TCX: A RISC Style Tensor Computing Extension and a Programmable Tensor Processor

Neural network processors and accelerators are domain-specific architectures deployed to solve the high computational requirements of deep learning algorithms. This article proposes a new instruction set extension for tensor computing, TCX, using Reduced Instruction Set Computer (RISC) instructions enhanced with variable length tensor extensions. It features a multi-dimensional register file, dimension registers, and fully generic tensor instructions. It can be seamlessly integrated into existing RISC Instruction Set Architectures and provides software compatibility for scalable hardware implementations. We present a tensor accelerator implementation of the tensor extensions using an out-of-order RISC microarchitecture. The tensor accelerator is scalable in computation units from several hundred to tens of thousands. An optimized register renaming mechanism is described that allows for many physical tensor registers without requiring architectural support for large tensor register names. We describe new tensor load and store instructions that reduce bandwidth requirements using tensor dimension registers. Implementations may balance data bandwidth and computation utilization for different types of tensor computations such as element-wise, depthwise, and matrix-multiplication. We characterize the computation precision of tensor operations to balance area, generality, and accuracy loss for several well-known neural networks. The TCX processor runs at 1 GHz and sustains 8.2 Tera operations per second using a 4,096 multiply-accumulate compute unit. It consumes 12.8 mm 2 while dissipating 0.46W/TOPs in TSMC 28-nm technology.

DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR

DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR

Development and Performance Evaluation of Photovoltaic (PV) Evaluation and Fault Detection System Using Hardware-in-the-Loop Simulation for PV Applications

This paper originally presents a photovoltaic (PV) evaluation and fault detection (PVEFD) system for PV applications based on the Internet of Things (IoT) technology. The PVEFD system consists of an STM32F103C8T6 chip with a 32-bit Arm Cortex-M3 reduced instruction set computer (RISC) and 12-bit resolution analog-to-digital converter (ADC) to measure important parameters of PV applications, such as solar irradiance as well as the back-surface cell temperature, operating voltage, and output current of PV devices. The measured data of irradiance as well as back-surface cell temperature and operating voltage of PV devices are then fed into a built-in PV model in the on-chip Arm Cortex-M3 RISC for hardware-in-the-loop (HIL) simulation to obtain the simulated output current and power of PV devices. The resulting data are transmitted to a cloud server for remote monitoring and automatic warning function through a Raspberry PI 3 module and WiFi network. The simulation results are compared with in-field measurement data from PV modules and displayed on a human-machine interface (HMI) and an Android app. The results of the study illustrated that the proposed system features high accuracy and sufficient confidence. Furthermore, the fault detection function through the built-in HIL simulation function in PV systems was validated. Therefore, the proposed system is a small, compact, and cost-effective HIL-on-chip machine for remote surveillance of PV power systems.

Efficient Reverse Intersystem Crossing in Carbene‐Copper‐Amide TADF Emitters via an Intermediate Triplet State

AbstractThe mechanism behind reverse intersystem crossing (rISC) in metal‐based TADF emitters is still under debate. Thermal rISC necessitates small singlet/triplet energy gaps as realized in donor‐acceptor systems with charge‐transfer excited states. However, their associated spin‐orbit couplings are too small to account for effective rISC. Here, we report the first nonadiabatic dynamics simulation of the rISC process in a carbene‐copper(I)‐carbazolyl TADF emitter. Efficient rISC on a picosecond time scale is demonstrated for an initial triplet minimum geometry that exhibits a perpendicular orientation of the ligands. The dynamics involves an intermediate higher‐lying triplet state of metal‐to‐ligand charge transfer character (3MLCT), which enables large spin‐orbit couplings with the lowest singlet charge transfer state. The mechanism is completed in the S1 state, where the complex can return to a co‐planar coordination geometry that presents high fluorescence efficiency.

Efficient Reverse Intersystem Crossing in Carbene-Copper-Amide TADF Emitters via an Intermediate Triplet State.

The mechanism behind reverse intersystem crossing (rISC) in metal-based TADF emitters is still under debate. Thermal rISC necessitates small singlet/triplet energy gaps as realized in donor-acceptor systems with charge-transfer excited states. However, their associated spin-orbit couplings are too small to account for effective rISC. Here, we report the first nonadiabatic dynamics simulation of the rISC process in a carbene-copper(I)-carbazolyl TADF emitter. Efficient rISC on a picosecond time scale is demonstrated for an initial triplet minimum geometry that exhibits a perpendicular orientation of the ligands. The dynamics involves an intermediate higher-lying triplet state of metal-to-ligand charge transfer character (3 MLCT), which enables large spin-orbit couplings with the lowest singlet charge transfer state. The mechanism is completed in the S1 state, where the complex can return to a co-planar coordination geometry that presents high fluorescence efficiency.

Smart Multi-Agent Framework for Automated Audio Testing

With the widespread use of embedded software in consumer electronics, automotive industry, medical devices, and industrial environments, embedded software testing is gaining significance as an indispensable part of development and deployment of embedded products. With more than 20 years of research, development, and testing of various consumer technologies and products based on digital signal processors (DSPs) and advanced reduced instruction set computers (ARMs), we obtained insight into typical embedded development process and testing, and the pros and cons of various testing approaches and environments. In this paper, we propose the Smart Multi-Agent Framework based on IoT and Jenkins agents, customised for audio technologies in the Home Audio domain. We evaluated our solution on several complex immersive audio technologies implemented on a multicore DSP. Our uniform, customised, fully automated approach proved to be time efficient, error resilient, easy to replicate and use across all development, certification, and deployment phases of the product life cycle.

P4 and NetFPGA-Based Secure In-Network Computing Architecture for AI-Enabled Industrial Internet of Things

This article proposes a secure in-network computing system based on a simple reduced instruction set architecture, which can be used for processing artificial intelligence and machine learning models in network devices, in an AI-based Industrial Internet of Things (IoT) system. The architecture exploits the capabilities of upcoming generations of packet processing pipelines in programmable network switches. This instruction set enables processing of data at multiple terabits-per-second, which is beyond the processing power of current servers. Instructions for regular expressions, basic arithmetic, and logical operations are defined as a proof of concept. A packet containing both instruction and data blocks is presented as an input to the pipeline by bundling both the function and its arguments into the packet. The primary challenge in opening up network switches for executing a user-defined code is security. In this context, this article presents a secure execution model (SEM), which provides additional levels of security by deliberately disallowing memory allocation and modifications to persistent state of the network switch. Furthermore, real-life use cases are presented in this article to demonstrate the utility of the proposed instruction set architecture, as also applicable to IoT data processing. This instruction set is implemented in the programming protocol-independent packet processors language, verified on a mininet-based software switch and demonstrated on Xilinx NetFPGA SUME boards. The performance results show line rate packet processing with zero packet loss, at 10 Gb/s, and average packet latency of 3.66 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{s}$ </tex-math></inline-formula> .

Bringing Compiling Databases to RISC Architectures

Current hardware development greatly influences the design decisions of modern database systems. For many modern performance-focused database systems, query compilation emerged as an integral part and different approaches for code generation evolved, making use of standard compilers, general-purpose compiler libraries, or domain-specific code generators. However, development primarily focused on the dominating x86-64 server architecture; but neglected current hardware developments towards other CPU architectures like ARM and other RISC architectures. Therefore, we explore the design space of code generation in database systems considering a variety of state-of-the-art compilation approaches with a set of qualitative and quantitative metrics. Based on our findings, we have developed a new code generator called FireARM for AArch64-based systems in our database system, Umbra. We identify general as well as architecture-specific challenges for custom code generation in databases and provide potential solutions to abstract or handle them. Furthermore, we present an extensive evaluation of different compilation approaches in Umbra on a wide variety of x86-64 and ARM machines. In particular, we compare quantitative performance characteristics such as compilation latency and query throughput. Our results show that using standard languages and compiler infrastructures reduces the barrier to employing query compilation and allows for high performance on big data sets, while domain-specific code generators can achieve a significantly lower compilation overhead and allow for better targeting of new architectures.

A theoretical study on the influence of N-containing heterocyclic ligands on the luminescence mechanisms (phosphorescence or TADF) of Au (III) complexes

Au (III) complexes display remarkable emission properties in OLEDs materials due to the high-performance emitters in recent years. Explaining microscopic mechanisms of the luminescence process clearly remain a challenge. The intersystem crossing between the singlet excited state and the triplet excited state in the metal complexes systems plays a central role in determining the fate of excitons and various luminescence pathways. For the planar tridentate coordination complexes of Au (III), it remains unclear what are the key factors that affect the luminescent pathways and thus the quantum efficiency. This work uncovers the relationship between the intersystem crossing processes (include ISC and RISC) and electronic structures of chelated ligands in the Au ( III ) complexes, which is supported by the quantum-chemical calculations. It is found that the modification of strong electron-donating groups (such as –NMe 2 , -NPh 2 ) may reduce the vibration coupling effect and energy gap (Δ E ST ), then open the thermal equilibrium channel, and finally obtain higher quantum yield TADF emitter through the fluorescence process. But the complex that has carbazole group in the auxiliary ligand still can't undergo the RISC process. These may be caused by the various electron delocalization and transition type result from different auxiliary ligands mediated by the N 2 atom. Moreover, the vibration analyses for the phosphorescence emision show that the vibration modes, which make significantly contribute to the reorganization energy, mainly come from the CˆNˆC ligand. While for TADF emission, that is from the auxiliary ligand. This work presents a deep insight into the luminescent mechanism and the key factors affected by the regulation of the ligands in the Au (III) complexes, and provides valuable theoretical basis and reference for the synthesis and design of TADF materials. • The higher SOC effect does not necessarily lead to the TADF process. • The modification of strong electron-donating may reduce the vibration coupling effect and energy gap Δ E ST , finally obtain higher quantum yield TADF emitter through the fluorescence process. • Adding the carbazole group in the auxiliary ligand can enhance the contribution of the CˆNˆC ligand on the reorganization energy.

Enhanced reverse inter-system crossing process of charge-transfer stated induced by carrier balance in exciplex-type OLEDs

The reverse inter-system crossing (RISC, CT&lt;sup&gt;3&lt;/sup&gt; → CT&lt;sup&gt;1&lt;/sup&gt;) process in charge transfer (CT&lt;sup&gt;1&lt;/sup&gt; and CT&lt;sup&gt;3&lt;/sup&gt;) states is an effective approach to improving the energy utilization rate of excited states, and precise control and full use of the RISC process have important scientific significance and application prospect for fabricating and realizing the efficient exciplex-type organic light-emitting diodes (OLEDs). The conventional exciplex-type OLEDs based on m-MTDATA: Bphen have received extensive attention among researchers owing to the fact that the energy difference between CT&lt;sup&gt;1&lt;/sup&gt; and CT&lt;sup&gt;3&lt;/sup&gt; around zero promotes the efficient occurrence of RISC process. But up to now, only transient photoluminescence can infer the existence of RISC process in experiment, which is quite unfavorable for the comprehensive understanding and application of this process to design high-performance OLEDs. Fortunately, in this paper, a series of balanced and unbalanced exciplex-based devices are prepared by changing the donor-acceptor blending ratio in the emitting layer (&lt;i&gt;x&lt;/i&gt;% &lt;i&gt;m&lt;/i&gt;-MTDATA:&lt;i&gt;y&lt;/i&gt;% Bphen; &lt;i&gt;x&lt;/i&gt;%, &lt;i&gt;y&lt;/i&gt;% is the weight percent) and the carrier density flowing through the device. The RISC process of CT states is directly observed via analyzing fingerprint magneto-conductance (MC) traces of the balanced device at room temperature, and the balanced device has higher electroluminescence (EL) efficiency than the unbalanced device. Specifically, the low-field MC curves of unbalanced device only show an inter-system crossing (ISC) line shape, whereas those from the balanced exciplex device present an RISC line shape at low bias-current and the conversion into an ISC line shape with the further increase of bias current. The line shape transition from RISC to ISC is attributed to the triplet-charge annihilation (TQA) process caused by excessive charge carries under high bias current. Combining the physical microscopic mechanism of device, the above-mentioned MC curves of various exciplex devices can be explained as follows: under the same bias current, extra holes or electrons are generated in the emitter layer of unbalanced devices due to the mismatch of donor-acceptor molecular concentrations. These superfluous holes or electrons will react with the CT&lt;sup&gt;3&lt;/sup&gt; state, which aggravates the TQA process in the device and weakens the RISC process in which the CT&lt;sup&gt;3&lt;/sup&gt; state participates. That is to say, there are strong TQA process and weak RISC process in unbalanced exciplex device. Contrarily, the strong RISC process and weak TQA process in the balanced exciplex device are beneficial to the occurrence of delayed fluorescence, resulting in its EL efficiency higher than that of the unbalanced device. This work not only deepens the physical understanding of the influence of donor-acceptor blending ratio on the carrier balance in exciplex devices, but also paves the way for designing highly efficient OLED by fully employing the RISC process of balanced device.

A Review of Vedic Mathematics for the Design of High-Speed Arithmetic RISC Processors

Vedic Mathematics is a collection of techniques and concepts developed from ancient Indian mathematical books known as the Vedas. These strategies are designed to make different mathematical computations easier and faster. High-throughput RISC Processor Design, on the other hand, includes the creation of processors that prioritize the execution of a high number of instructions per unit of time. If there have been breakthroughs relating to Vedic Mathematics and High-Throughput RISC Processor Design, it would be intriguing to investigate how these old mathematical ideas may be utilized to improve the efficiency of current processor designs. Give a summary of the work, stressing the potential benefits and drawbacks of incorporating Vedic Mathematics concepts into the design of High-Throughput RISC computers. Introduce Vedic Mathematics and High-Throughput RISC Processor Design separately. Explain briefly why you're looking at incorporating Vedic Mathematics into CPU architecture. Outline key Vedic Mathematics concepts that may be applied to processor design. What distinguishes these ideas from typical mathematical approaches Provide an overview of the fundamental ideas and issues involved in the design of high-throughput RISC processors. Emphasize the critical areas for improvement and integrating principles from Vedic Mathematics into Processor Architecture: Investigate the use of Vedic Mathematics principles in processor architecture to discuss how these concepts may be utilized to solve specific problems or improve aspects of high-throughput RISC architectures. The importance of multipliers in Arithmetic Unit performance is underlined. The incorporation of Vedic Science, an ancient mathematical system comprised of 16 Sutras, implies a fresh method for arithmetic computations. The suggestion comprises optimizing the Vedic multiplier type Urdhva Triyakbhyam by substituting Convey Save Viper for the usual carry. This is done to reduce delays caused by standard adders and incomplete products aspire to outperform traditional designs in terms of speed. The explicit data on the speed gains is obtained and how they were assessed will bolster the claims and utilization of the proposed proficient Vedic multiplier in the number juggling module of the RISC processor. In addition, stating its application in the field of digital signal processing (DSP) broadens the scope of work. Validation of RTLs and FPGAs for the Register-Transfer Level (RTL) implementation of the proposed Math Unit in VHDL, paired with simulation using Xilinx ISE EDA tools, is a useful step in verifying the design. Validation on an FPGA device, especially a Vertex-IV, provides credibility to the suggested solution.

Adaptive Emulation Framework for Multi-Architecture IoT Firmware Testing

Internet of things (IoT) devices are being increasingly used in numerous areas. However, the low priority on security and various IoT types have made these devices vulnerable to attacks. To prevent this, recent studies have analyzed firmware in an emulation environment that does not require actual devices and is efficient for repeated experiments. However, these studies focused only on major firmware architectures and rarely considered exotic firmware. In addition, because of the diversity of firmware, the emulation success rate is not high in terms of large-scale analyses. In this study, we propose the adaptive emulation framework for multi-architecture (AEMA). In the field of automated emulation frameworks for IoT firmware testing, AEMA considers the following issues: (1) limited compatibility for exotic firmware architectures, (2) emulation instability when configuring an automated environment, and (3) shallow testing range resulting from structured inputs. To tackle these problems, AEMA can emulate not only major firmware architectures but also exotic firmware architectures not previously considered, such as Xtensa, ColdFire, and reduced instruction set computer (RISC) version five, by implementing a minority emulator. Moreover, we applied the emulation arbitration technique and input keyword extraction technique for emulation stability and efficient test case generation. We compared AEMA with other existing frameworks in terms of emulation success rates and fuzz testing. As a result, AEMA succeeded in emulating 864 out of 1,083 overall experimental firmware and detected vulnerabilities at least twice as fast as the experimental group. Furthermore, AEMA found a 0-day vulnerability in real-world IoT devices within 24 h.

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge

DIgital-ANAlog (DIANA), a heterogeneous multi-core accelerator, combines a reduced instruction set computer - five (RISC-V) host processor with an analog in-memory computing (AIMC) artificial intelligence (AI) accelerator and a digital reconfigurable deep neural network (DNN) accelerator in a single system-on-chip (SoC) to support a wide variety of neural network (NN) workloads. AIMC cores can bring extreme computational parallelism and efficiency at the expense of accuracy and dataflow flexibility. Digital AI co-processors, on the other hand, guarantee accuracy through deterministic compute, but cannot achieve the same computational density and efficiency. DIANA exploits this fundamental tradeoff by integrating both types of cores in a shared and optimized memory system, to enable seamless execution of the workloads on the parallel cores. The system’s performance benefits further from pipelined parallel execution across both accelerator cores and enhanced AIMC spatial unrolling techniques, leading to drastically reduced execution latency and reduced memory footprints. The design has been implemented in a 22-nm technology and achieves peak efficiencies of 600 TOP/s/W for the AIMC core (I/W/O: 7/1.5/6 bit) and 14 TOP/s/W (I/W/O: 8/8/8 bit) for the digital accelerator, respectively. End-to-end performance evaluation of CIFAR-10 and ImageNet classification workloads is carried out on the chip, reporting 7.02 and 5.56 TOP/s/W, respectively, at the system level.

A Blockchain-Based Architecture for Securing Industrial IoTs Data in Electric Smart Grid

There are numerous internet-connected devices attached to the industrial process through recent communication technologies, which enable machine-to-machine communication and the sharing of sensitive data through a new technology called the industrial internet of things (IIoTs). Most of the suggested security mechanisms are vulnerable to several cybersecurity threats due to their reliance on cloud-based services, external trusted authorities, and centralized architectures; they have high computation and communication costs, low performance, and are exposed to a single authority of failure and bottleneck. Blockchain technology (BC) is widely adopted in the industrial sector for its valuable features in terms of decentralization, security, and scalability. In our work, we propose a decentralized, scalable, lightweight, trusted and secure private network based on blockchain technology/smart contracts for the overhead circuit breaker of the electrical power grid of the Al-Kufa/Iraq power plant as an industrial application. The proposed scheme offers a double layer of data encryption, device authentication, scalability, high performance, low power consumption, and improves the industry’s operations; provides efficient access control to the sensitive data generated by circuit breaker sensors and helps reduce power wastage. We also address data aggregation operations, which are considered challenging in electric power smart grids. We utilize a multi-chain proof of rapid authentication (McPoRA) as a consensus mechanism, which helps to enhance the computational performance and effectively improve the latency. The advanced reduced instruction set computer (RISC) machines ARM Cortex-M33 microcontroller adopted in our work, is characterized by ultra-low power consumption and high performance, as well as efficiency in terms of real-time cryptographic algorithms such as the elliptic curve digital signature algorithm (ECDSA). This improves the computational execution, increases the implementation speed of the asymmetric cryptographic algorithm and provides data integrity and device authenticity at the perceptual layer. Our experimental results show that the proposed scheme achieves excellent performance, data security, real-time data processing, low power consumption (70.880 mW), and very low memory utilization (2.03% read-only memory (RAM) and 0.9% flash memory) and execution time (0.7424 s) for the cryptographic algorithm. This enables autonomous network reconfiguration on-demand and real-time data processing.

A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance

While neural network (NN) accelerators are being significantly developed in recent years, CPU is still essential for data management and pre-/post-processing of accelerators in a commonly used heterogeneous architecture, which usually contains an NN accelerator and a processor core with data transfer performed by direct memory access (DMA) engine. This work presents a special neural processor, referred to as a systolic neural CPU processor (SNCPU), which is a unified architecture combining deep learning and general-purpose computing for fifth-generation of reduced instruction set computer (RISC-V) to improve end-to-end performance for machine learning (ML) tasks compared with a common heterogeneous architecture with CPU and accelerator. With 64%–80% processing elements (PEs) logic reuse and 10% area overhead, SNCPU can be configured into ten RISC-V CPU cores. Special bi-directional dataflow and four different working modes are developed to enhance the utilization of deep NN (DNN) accelerator and eliminate the expensive data transfer between CPU and DNN accelerator in existing heterogeneous architecture. A 65-nm test chip was fabricated demonstrating a 39%–64% performance improvement on end-to-end image classification tasks for ImageNet, Cifar10, and MNIST datasets with over 95% PE utilization and up to 1.8TOPs/W power efficiency.

TCN-CUTIE: A 1,036-TOp/s/W, 2.72-µJ/Inference, 12.2-mW All-Digital Ternary Accelerator in 22-nm FDX Technology

Tiny machine learning (TinyML) applications impose µJ/inference constraints, with a maximum power consumption of tens of megawatt. It is extremely challenging to meet these requirements at a reasonable accuracy level. This work addresses the challenge with a flexible, fully digital ternary neural network (TNN) accelerator in a reduced instruction set computer-five (RISC-V)-based System-on-Chip (SoC). Besides supporting ternary convolutional neural networks, we introduce extensions to the accelerator design that enable the processing of time-dilated temporal convolutional neural networks (TCNs). The design achieves 5.5-µJ/inference, 12.2 mW, 8,000 inferences/s at 0.5 V for a dynamic vision sensor (DVS)-based TCN and an accuracy of 94.5%, and 2.72-µJ/inference, 12.2 mW, 3,200 inferences/s at 0.5 V for a nontrivial 9-layer, 96 channels-per-layer convolutional network with CIFAR-10 accuracy of 86%. The peak energy efficiency is 1,036 TOp/s/W, outperforming the state-of-the-art silicon-proven TinyML quantized accelerators by 1.67× while achieving competitive accuracy.