Ring VCOs Research Articles

A 1.2GHz Frequency Range, 153.4 dBc/Hz FoM, low Phase Noise, Current Starved Multi-Path Ring VCO

This article describes the design of a low power, low phase noise, multi-Path ring VCO (MPRVCO) in 90nm CMOS process. The proposed oscillator achieves a tuning range of 1.2GHz operating at 1.65 GHz center frequency, with reduced phase noise of -87.3dBc/Hz at 1MHz offset. The proposed MPRVCO achieves a FoM of 153.4dBc/Hz, consuming 0.657mW power at 1.65GHz frequency. The proposed VCO utilizes Current starving technique for frequency variation. Sub-threshold transistor is used to obtain monotonic and linear frequency tuning characteristics. The proposed VCO is one of the very few Current Starved ring VCOs capable of producing such low phase noise in 90nm CMOS process while operating in GHz frequency range

Phase noise reduction by resistor abutment in differential ring VCOs

Phase noise reduction by resistor abutment in differential ring VCOs

Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications

PurposeSeveral ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors.Design/methodology/approachThis study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency.FindingsAs a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption.Originality/valueSeveral new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs

This brief studies comparatively the different 8-phase feedforward-coupling (FC) ring voltage-controlled oscillators in terms of their oscillation modes, oscillation frequency, and phase noise. Among the 3 feasible topologies, the one with sub-feedback loops containing 2 direct-path inverters + 1 feedforward-path inverter (i.e., 2D + 1F) can achieve a better phase noise than the common 4D + 1F topology at the same frequency and power budget. It is also shown that the bimodal oscillation problem of the 2D + 1F topology can be eliminated by inserting an auxiliary FC path. Prototyped in 65-nm CMOS, the proposed 2D + 1F topology at 3.1 GHz shows a phase noise of −95.1 dBc/Hz at a 1-MHz offset, corresponding to a 159.9-dBc/Hz figure-of-merit that is 4.2 dB higher than the common 4D + 1F topology.

Study and analysis of DR-VCO for rad-hardness in type II third order CPLL

In this paper, suitability of differential ring VCO designed using 90 nm CMOS process for the SET environment is studied for number of delay stages ranging from three to eleven operating at 2.6 GHz frequency. Effect of increasing the number of VCO delay cell stages to suppress SET strike sensitivity of oscillator has been studied for Linear Energy Transfer (LET) values between 20 and 200 MeV-cm2/mg. To further validate the relation between the number of stages used in VCO architecture and SET tolerance level, the differential ring VCOs are tested within a type II 3rd order CPLL operating at the same frequency. Circuit simulations show that the PLL performance parameters: settling behaviour and error cycles of PLL are strongly correlated to the number of delay stages used in the VCO. The error cycles produced by CPLL with 11 stage VCO in response to SET hit with LET value of 200 MeV-cm2/mg achieves 53% improvement compared to CPLL with 3 stage VCO.

Phase displacement study in MOSFET based ring VCOs due to heavy-ion irradiation using 3D-TCAD and circuit simulation

This paper analyzes the radiation tolerance of both single ended and differential ring VCO in the presence of SET in 90nm CMOS process technology. Phase displacement is an important metric in assessing the susceptibility and suitability of any frequency synthesizer in the presence of SET. Through device level characterization using Synopsys TCAD and extensive circuit level simulation and verification, for heavy ion dosage with LET between 20 ((MeV-cm2)/mg) and 200 ((MeV-cm2)/mg), the current starved differential delay cell based 3-stage differential ring VCO exhibits a phase displacement improvement of around 20% compared to a current starved inverter based single ended ring VCO oscillating at 420MHz. When the number of stages in differential ring VCO are increased from 3 to 7 the phase displacement is reduced by a factor of 57%. However, to achieve similar phase displacement improvement in inverter based single ended ring VCO required in excess of 15 stages. The active area for the differential ring VCO decreases by almost 40% as the number of stages increases.

A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL

This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer. In order to reduce the quantization noise, operating frequency of ΔΣ modulator (DSM) is increased by using an intermediate output of feedback divider. A PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider. Prototype implemented in a 0.13 μm CMOS using ring VCOs achieves 26.3 dB of quantization noise suppression while consuming 15.2 mW and occupying 0.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Recent Advances in Delay Cell VCOs [Application Notes

In this article, a review of commonly used delay cell techniques in ring VCO design was covered. Design limitations such as area, power, jitter, and phase noise performance were compared for ring and LC VCOs. These parameters were compared for several delay cell topologies throughout the paper. The tunable and flexible bandwidth criterion combined with low-noise characteristics, low power, and small-area properties are the main concern of industrial engineers in design ing and choosing a proper resonator topology suitable for their respective applications. We described a num ber of the most common delay cell structures to make it easier for engineers to have a wider perspective on ring resonators.