Study and analysis of DR-VCO for rad-hardness in type II third order CPLL

Abstract

In this paper, suitability of differential ring VCO designed using 90 nm CMOS process for the SET environment is studied for number of delay stages ranging from three to eleven operating at 2.6 GHz frequency. Effect of increasing the number of VCO delay cell stages to suppress SET strike sensitivity of oscillator has been studied for Linear Energy Transfer (LET) values between 20 and 200 MeV-cm2/mg. To further validate the relation between the number of stages used in VCO architecture and SET tolerance level, the differential ring VCOs are tested within a type II 3rd order CPLL operating at the same frequency. Circuit simulations show that the PLL performance parameters: settling behaviour and error cycles of PLL are strongly correlated to the number of delay stages used in the VCO. The error cycles produced by CPLL with 11 stage VCO in response to SET hit with LET value of 200 MeV-cm2/mg achieves 53% improvement compared to CPLL with 3 stage VCO.