Ring Oscillator Research Articles

Impact of low-temperature and low-pressure mild oxidation after plasma solidification on electrical properties and reliability in ultra-thin SiON MOSFETs

The impact of different SiON manufacturing processes on performance and reliability behaviors has been investigated for the MOSFETs. The performance of devices composed of an ultrathin SiON film fabricated by the novel low-temperature and low-pressure mild oxidation after the plasma solidification (LLMOPS) method can be enhanced compared to conventional processes, which is attributed to the increased mobility. It is observed from secondary ion mass spectrometry analysis that the distribution of nitrogen with the LLMOPS process moves toward the upper surface of SiON. As a result, the p-MOSFET manufactured by the LLMOPS process exhibits lower electrical performance degradation during the NBTI stress, indicating that a reduction in nitrogen concentration at the Si/SiO2 interface contributes to improving NBTI behavior. It is also demonstrated that the inhibition of NBTI phenomena enhances the frequency stability on the ring oscillator with circuit simulation. Thus, the LLMOPS process is a promising approach to improve the performance and reliability of MOSFETs in mass production.

Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors.

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage.

The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

Stacked Si Nanosheets Gate-All-Around Transistors with Silicon-on-Nothing Structure for Suppressing Parasitic Effects and Improving Circuits’ Performance

We propose a novel silicon-on-nothing (SON) structure with an air sub-fin for suppressing the parasitic channel effects on stacked Si nanosheets (NS) gate-all-around (GAA) transistors and a systematic investigation is carried out by 3D TCAD simulation. The SON structure could be fabricated using a backside selective etching technique. The proposed SON NSFETs with a designed air sub-fin structure demonstrates systematic advantages, including 40% off-state current reduction in the sub-channel, and 51.37% promotion for on-off current ratio (ION/IOFF) and 7.04% reduction in effective capacitance. Moreover, there is approximately 21.62% power reduction under the same frequency, and about 16.30% energy reduction under the same delay in 17-stage ring oscillators (ROs). The SON NSFETs-based 6T-SRAM exhibits decreased read time and write time by 14.66% and 67.53%, respectively, compared with those of the conventional GAA NSFETs-based 6T-SRAM.

783 MHz fundamental repetition rate all-fiber ring laser mode-locked by carbon nanotubes

We demonstrate a 783 MHz fundamental repetition rate mode-locked Er-doped all-fiber ring laser with a pulse width of 623 fs. By using carbon nanotubes saturable absorber, a relatively low self-starting pump threshold of 108 mW is achieved. The laser has a very compact footprint less than 10 cm × 10 cm, benefiting from the all-active-fiber cavity design. The robust mode-locking is confirmed by the low relative intensity noise and a long-term stability test. We propose a new scheme for generating high repetition rate femtosecond optical pulses from a compact and stable all-active-fiber ring oscillator.

Hopf bifurcations of twisted states in phase oscillators rings with nonpairwise higher-order interactions

Synchronization is an essential collective phenomenon in networks of interacting oscillators. Twisted states are rotating wave solutions in ring networks where the oscillator phases wrap around the circle in a linear fashion. Here, we analyze Hopf bifurcations of twisted states in ring networks of phase oscillators with nonpairwise higher-order interactions. Hopf bifurcations give rise to quasiperiodic solutions that move along the oscillator ring at nontrivial speed. Because of the higher-order interactions, these emerging solutions may be stable. Using the Ott–Antonsen approach, we continue the emergent solution branches which approach anti-phase type solutions (where oscillators form two clusters whose phase is π apart) as well as twisted states with a different winding number.

P‐28: High‐speed Oscillator using Polycrystalline InGaO TFTs by Spray Pyrolysis on Polyimide Substrate for Flexible Electronics

We demonstrate high‐performance coplanar thin film transistors (TFTs) on polyimide (PI) substrate, with very thin polycrystalline InGaO (poly‐IGO) thin films deposited by spray‐pyrolysis. The TFTs exhibit saturation mobility (µSAT) of ~39.25 ± 0.73 cm2 V−1 s−1, with excellent uniformity and stable bias stabilities (ΔVTH = +0.3 V for PBTS, ΔVTH = −0.3 V for NBTS). The 7‐stage ring oscillator made of the corresponding TFTs exhibits a very high oscillation frequency of 9.09 MHz at VDD of 15 V with ultra‐low propagation delay time of 7.86 ns/stage.

Generative Modeling of Semiconductor Devices for Statistical Circuit Simulation

Statistical simulation is a necessary step in integrated circuit design since it provides a realistic picture of the circuit’s behavior in the presence of manufacturing process variations. When some of the circuit components lack an accurate analytical model, as is often the case for emerging semiconductor devices or ones working at cryogenic temperatures, an approximation model is necessary. Such models are usually based on a lookup table or artificial neural network individually fitted to measurement data. If the number of devices available for measurement is limited, so is the number of approximation model instances, which renders impossible a reliable statistical circuit simulation. Approximation models using the device’s physical parameters as inputs have been reported in the literature but are only useful if the end user knows the statistical distributions of those parameters, which is not always the case. The solution proposed in this work uses a type of artificial neural network called the variational autoencoder that, when exposed to a small sample of I-V curves under process variations, captures their essential features and subsequently generates an arbitrary number of similarly disturbed curves. No knowledge of the underlying physical sources of these variations is required. The proposed generative model trained on as few as 20 instances of a MOSFET is shown to precisely reproduce the period and power consumption distributions of a ring oscillator built with these MOSFETs.

Eight In. Wafer-Scale Epitaxial Monolayer MoS2.

Large-scale, high-quality, and uniform monolayer molybdenum disulfide(MoS2) films are crucial for their applications in next-generation electronics and optoelectronics. Epitaxy is a mainstream technique for achieving high-quality MoS2 films and is demonstrated at a wafer scale up to 4-in. In this study, the epitaxial growth of 8-in. wafer-scale highly oriented monolayer MoS2 on sapphire is reported as with excellent spatial homogeneity, using a specially designed vertical chemical vapor deposition (VCVD) system. Field effect transistors (FETs) based on the as-grown 8-in. wafer-scale monolayer MoS2 film are fabricated and exhibit high performances, with an average mobility and an on/off ratio of 53.5 cm2 V-1 s-1 and 107, respectively. In addition, batch fabrication of logic devices and 11-stage ring oscillators are also demonstrated, showcasing excellent electrical functions. This work may pave the way of MoS2 in practical industry-scale applications.

Circuit Level Implementation of Negative Capacitance Source Pocket Double Gate Tunnel FET for Low Power Applications

This manuscript presents a pioneering study on enhancing analog and radio frequency performance through the implementation of negative capacitance source pocket double gate tunnel field-effect transistor. By integrating a ferroelectric material into the gate stack and introducing a fully depleted n-type pocket near the source/channel junction, we achieved significant enhancements in key metrics such as ON current (ION), switching ratio, subthreshold swing (SS), and various analog/RF parameters like transconductance (gm), cutoff frequency (fT) when compared to existing literature. Additionally, we extend our analysis to circuit-level applications such as inverter and 5-stage ring oscillator. Our findings reveal an impressive inverter delay of 1.09 ps with a gain of 104, as well as a ring oscillator operating at a frequency of 500 GHz. These results position the proposed device as an ideal candidate for high-speed, low-power applications.

Timing Evaluation of Passive Transmission Line by RSFQ Ring Oscillator

Timing Evaluation of Passive Transmission Line by RSFQ Ring Oscillator

Covert-channels in FPGA-enabled SmartSSDs

Cloud computing providers today offer access to a variety of devices, which users can rent and access remotely in a shared setting. Among these devices are SmartSSDs, which are solid-state disks (SSD) augmented with an FPGA, enabling users to instantiate custom circuits within the FPGA, including potentially malicious circuits for power and temperature measurement. Normally, cloud users have no remote access to power and temperature data, but with SmartSSDs they could abuse the FPGA component to instantiate circuits to learn this information. Additionally, custom power waster circuits can be instantiated within the FPGA. This paper shows for the first time that by leveraging ring oscillator sensors and power wasters, numerous covert-channels in FPGA-enabled SmartSSDs could be used to transmit information. This work presents two channels in single-tenant setting (SmartSSD is used by one user at a time) and two channels in multi-tenant setting (FPGA and SSD inside SmartSSD is shared by different users). The presented covert channels can reach close to 100% accuracy. Meanwhile, bandwidth of the channels can be easily scaled by cloud users renting more SmartSSDs as the bandwidth of the covert channels is proportional to number of SmartSSD used.

Performance Evaluation of Nano-scale Core–Shell Junctionless FETs in the Designing of Ultralow-Power Inverter and Ring Oscillator

Performance Evaluation of Nano-scale Core–Shell Junctionless FETs in the Designing of Ultralow-Power Inverter and Ring Oscillator

Monolithic three-dimensional hafnia-based artificial nerve system

Artificial nerve systems that mimic the tactile perception ability of human skin could be adopted in the realization of devices for a hyperconnected society, including prosthetic devices, interfaces for virtual reality, and smart sensors. The system consists of a pressure sensor, memory, and signal processing circuit, which possess the capability of generating sensory neuron-like signals. Although technological advances have been made in semiconductor-based memory and transistors over the decades, sensor technology is still relying on micro-electromechanical systems, which are hard to realize miniaturization/high-density and high-performance technology. Here, we demonstrate a monolithic three-dimensional integrated artificial nerve on the basis of ferroelectric HfxZr1-xO2 for use in the core element of neuromorphic memory and a self-powered piezoelectric pressure sensor. The morphotropic phase boundary (MPB) state of hafnia film was formed between orthorhombic and tetragonal phases for high piezoelectric performance. The MPB-based sensor was integrated with self-rectifying ferroelectric tunnel junction memory and silicon-based ring oscillator. We realized a frequency-modulated pulse-like synaptic signal with pressure detection ability over a wide range of 1–50 kPa and a good sensitivity of 0.35 mV/kPa. Also, we demonstrate the real-time frequency-modulated operation of the artificial nerve system by adjusting the functional properties of the hafnia films.

Numerical Simulation, Electrostatic and Physical Compact Modeling of C8-BTBT-C8 Organic Thin Film Transistor

This paper presents numerical simulation and compact modeling of 2,7-Dioctyl {1} benzothieno {3,2-b}{1} benzothiophene (C8-BTBT-C8) organic semiconductor-based TFT. It shows the entire modeling process flow of this organic semiconductor (OSC) and tests the device realization using a ring oscillator. The paper comprises OSC characterisation, band-gap modeling, electrostatic modeling, and capacitance modeling. The TCAD model consists of the Hopping and Pool Frenkel premise and characterizes the Density of State (DOS) for traps in deep and tail states. The findings from this research provide valuable information for improving OTFT models, enhancing their predictive accuracy, and advancing the understanding of organic semiconductor device behavior. The electrostatics demonstrate device structure dependency

Fully active and highly reliable combined ring voltage controlled CMOS oscillator

Leveraging two types of enhanced delay stages to form an oscillation loop, results in a highly reliable CMOS ring oscillator versus external interventions. The idea is investigated via symbolic delay calculations and the HSPICE circuit simulator while 0.18 μm CMOS is exploited. Based on two described inverters, three-ring oscillators are presented. The two ones use only one type of delay stage while the third is combined using two basic inverters and a single current-starved inverter. The basic type inverter is the fastest while is sensitive to power supply and temperature variations. On the other hand, the sensitivity of the current starved inverter is acceptable but this delay stage shows a large delay time, reducing oscillation frequency. This work tries to address this tradeoff between speed and sensitivity by proposing an oscillation loop. The delay times analysis and simulation results verify the robust performance of the proposed oscillator.

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm2.

High-speed fluidic processing circuits for dynamic control of haptic and robotic systems.

Fluidic logic circuits simplify system design for soft robotics by eliminating bulky components while enabling operation in a range of hostile environments that are incompatible with electronics but at the expense of limited computational capabilities and response times on the order of seconds. This paper presents a four-terminal fluidic transistor optimized for fast switching times, reduced component count, low unit cost, and high reproducibility to achieve complex fluidic control circuits while maintaining flow rates of liters per minute. A ring oscillator using three fluidic transistors achieves oscillation frequencies up to a kilohertz with full signal propagation, tolerating billions of cycles without failure. Fundamental processor circuits like a full adder and a 3-bit analog-to-digital converter require just seven transistors each. A decode circuit drives a high-resolution soft haptic display with refresh times below the human perception threshold for latency, and an electronics-free control circuit performs closed-loop position control of a pneumatic actuator with disturbance rejection, demonstrating the value across domains.

SET sensitivity of a VCRO-based PLL for HL-LHC ATLAS HGTD

We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase Locked Loop (PLL) based on a Voltage Controlled Ring Oscillator (VCRO) under a proton beam. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) matrices for the High-Luminosity Large Hadron Collider (HL-LHC). We detail the methodology developed to study such events that could degrade the targeted time resolution of 35 ps per hit. Observed SET-induced phase jumps allow the estimation of the total cross-section of the PLL. The results are extrapolated to the HL-LHC radiation conditions.

Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit-compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves ∼1.18x and ∼9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON-current (2.74 mA/µm) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium-source L-shaped TFET by ∼7.89x and ∼4.81x, respectively. This study briefly examines the direct causes of the negative drain-induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NC-based devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON-current and voltage amplification, making them suitable for high-speed NCFET-based circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FET-based circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (fOSC) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15-stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by ∼2.19x and ∼16.69x in terms of fOSC, highlighting their superior performance in frequency-domain metrics. These findings demonstrate the potential of NCFET-based digital and mixed-signal circuits for high-performance integrated circuit designs.