RF Performance Research Articles

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

A computational approach to optimize the linearity in dual-gate InAlGaN/AlN/GaN HEMTs

Abstract This paper investigates the effect of the proposed dual gate structures in enhancing the linearity of InAlGaN/AlN/GaN high-electron-mobility transistors (HEMTs) using TCAD analysis. Through the comprehensive analysis of the dual gate structure with the additional gate placed between the gate-source (DG-GS) and gate-drain (DG-GD) regions, the impact on the linearity performance has been compared with that of a standard single gate (SG) structure. The dual gate configuration exhibits a flatter and broader transconductance (gm) profile than the single gate configuration. The reduction in the third-order intermodulation levels is confirmed with the polynomial fitting method. The fT/fmax of the DG-GS case is simulated to be 52/102 GHz, which shows that such configuration does not deteriorate the RF performance. Comprehensive simulations are carried out to study the device physics and assess the mechanism behind the linearity improvement. The large signal model has been developed to examine the large signal RF performance as well as linearity performance metrics. An improvement of 9.6 dB in the carrier-to-intermodulation (C/I) ratio and that of 2.4 degrees in the amplitude-to-phase modulation (AM-to-PM) at 6-dB backoff from Psat have been observed as compared to the SG configuration. Such characteristics have evidenced that the optimized dual-gate configuration with the second gate placed between the source and gate can effectively improve the linearity performance of the InAlGaN/AlN/GaN HEMT configurations.

NPDC structure double-channel N-polar E-mode GaN HEMTs: Innovations in enhancing RF and DC performance and mitigating trap effects

—High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) are favored for their exceptional performance in high-power and high-frequency applications. However, developing dual-channel HEMTs presents challenges due to spontaneous polarization effects and design complexities. This study introduces a novel N-polar E-mode GaN HEMT with a dual-channel structure, featuring recessed drain-source regions and non-alloyed ohmic contacts. TCAD simulations provide theoretical insights and optimization strategies for these structures, focusing on the combination of N-polar GaN and ultra-wide bandgap AlN barrier layers. The optimized device demonstrates a threshold voltage of +1.08 V and a 45.9 % increase in current density. The N-polar double-channel HEMT (NPDC-HEMT) exhibited a 55.75 % improvement in peak transconductance, with Ft increasing from 13.3 GHz to 30.1 GHz and Fmax from 63.7 GHz to 65.9 GHz. Further enhancement was achieved in the T-gate variant (NPDC-T-HEMT), with Ft reaching 52.6 GHz and Fmax 94.4 GHz. The dual-channel design effectively mitigated short-channel effects and current collapse, demonstrating the potential for high-power RF applications.

Fivefold increased power handling in waveguide UTC-PDs using dual-injection shared CPW PD-arrays

This work presents two circuit-based solutions to enhance the power handling capabilities of waveguide-integrated uni-travelling carrier photodetectors (WG-UTC-PDs). Compared to a baseline WG-UTC-PD, these solutions achieve a fivefold increase in photocurrent before thermal breakdown. First, dual-injection improves the optical power distribution within a baseline WG-UTC-PD, raising the photocurrent threshold before thermal breakdown. Second, an array of four optically parallel WG-UTC-PDs, electrically connected to a single coplanar waveguide (CPW) line, further increases the maximum photocurrent by distributing the input optical power across multiple PDs. The design omits a termination resistor, as the arrays do not rely on a traveling wave configuration, maximizing photocurrent without a 50% reduction of bandwidth. Both 4-PD single-injection and dual-injection arrays were designed, fabricated, and characterized. Compared to a baseline UTC-PD, with a maximum photocurrent of 1.8 mA at a 3 dB bandwidth of 55 GHz, the 4-PD single-injection circuit achieved 5.1 mA at 43 GHz. The dual-injection array further increased the photocurrent to 9.2 mA at a bandwidth of 35 GHz. Electrical reflection measurements confirmed the negative effects of CPW losses on RF performance. These power handling improvements enable compact, high-power integrated solutions for microwave photonics.

RF NEMS switches based on graphene for low pull-in voltage and excellent RF performance

This study introduces a novel graphene RF NEMS capacitive switch and conducts an extensive analysis of its RF performance using CST and COMSOL Multiphysics software. The switch’s characteristic impedance matching is accomplished through a coplanar waveguide (CPW) structure, incorporating a dielectric layer topped with conductive graphene beam electrodes. Simulation results reveal that the monolayer graphene RF NEMS switch maintains an insertion loss of 0.003 ~ 0.015 dB and an isolation greater than 40 dB across an ultra-wideband (UWB) frequency range of DC ~ 140 GHz. Moreover, the switch demonstrates a switching time of 4.03 ps at a pull-in voltage of 1 V. The performance of multilayer graphene RF NEMS switches was also evaluated. The study further investigates the operational mechanism of the graphene RF NEMS switch and performs finite element analysis on the proposed design. The graphene RF NEMS switch discussed herein offers significant advantages, including minimal size, lightweight, cost-effectiveness, low pull-in voltage, rapid response time, excellent RF performance, and reduced space consumption in circuitry. Its potential applications span a range from L to F bands, encompassing data storage, communication systems, sensors, remote sensing and military uses.

TCAD‐enabled machine learning framework for DC and RF performance evaluation of InGaAs sub‐channel DG‐HEMTs

AbstractThis research presents a machine learning (ML)‐based model that determines the DC and RF characteristics of InGaAs sub‐channel double gate high electron mobility transistors (DG‐HEMTs) to optimize the device structure. We employ technology computer‐aided design (TCAD) simulations to analyze the DC and RF performance of InGaAs sub‐channel DG‐HEMTs, generating a range of datasets by varying the material composition, layer width, and thickness of different layers in the device structure. We then train and optimize support vector regression (SVR) models using 5‐fold cross‐validation, varying the kernel function and degree parameters, and achieve better performance with the radial basis function (RBF) kernel. The simulated results indicate that the ML model predicts physical parameters more effectively than experimental analysis, offering a compact modeling solution that requires fewer computing resources than traditional methods.

Development and tests of the 499.8 MHz srf cryomodules for HEPS

A 499.8 MHz single-cell superconducting cavity has been proposed as the active third-harmonic cavity for the High Energy Photon Source (HEPS), a 6 GeV diffraction-limited synchrotron light source currently under construction in Beijing. Two 499.8 MHz cryomodules are required to provide a total of 3.5 MV of rf voltage and 400 kW of beam power. A mechanically enhanced cavity design, based on the original KEKB-type cavity, was developed to meet the specifications of HEPS. Three cryomodules have been assembled and subjected to horizontal tests. A comprehensive clean-assembly procedure was developed, resulting in excellent rf performance maintained from vertical tests to horizontal tests at cryogenic temperatures. The unloaded quality factors of all three modules exceeded 2.45×109 at 1.75 MV, significantly surpassing the design goal. No field emissions were observed throughout the tests. These are the highest-performing 500 MHz modules treated by buffered chemical polishing, also outperforming the average performance of their electropolished counterparts. Following dedicated analyses and multiple road tests, one cryomodule was successfully transported in its entirety from the test platform to the HEPS tunnel, with well-controlled accelerations on delicate components. Vacuum integrity and performance were well maintained. The module has been accelerating electron beams since August 2024 for the HEPS commissioning. This paper presents the design, fabrication, assembly, cryogenic tests, and transportation of the mechanically improved 499.8 MHz single-cell srf cryomodule.

Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance

This study focuses on the design and analysis of Junctionless (JL) NSFETs, with an emphasis on the influence of spacer materials and temperature variations. A different number of materials such as Air, SiO2, Si3N4, HfO2, and TiO2 are examined for sidewall spacer compatibility in the JL-NSFET. The same materials are used for dual material spacers with combinations of: Air+HfO2, Air+TiO2, SiO2+HfO2, and SiO2+TiO2. The investigations revealed that the usage of TiO2 material gives better digital and analog performance with reduced leakage currents and subthreshold swing (SS), higher on/off ratio, voltage gain of ∼79.7 dB. Exploring the dual-k spacers produced better analog performance, gate control and reduced leakages for SiO2+TiO2 owing to the usage of higher dielectric material towards the gate. Further, the reduction of temperature from 400 K to 250 K for all the single-k and dual-k spacer materials revealed that the designed JL-NSFET is a suitable candidate at lower temperatures to improve the digital and analog performance whereas not recommended for RF performance improvement. Moreover, the SiO2+HfO2 spacer-based CMOS inverter is noticed to have better gain (∼15 V/V), noise margin, and lower delays (∼5.1 ps) when compared to TiO2 spacer-based complementary metal oxide semiconductor inverter making it suitable for digital IC applications.

Piezoelectrically and Capacitively Transduced Hybrid MEMS Resonator with Superior RF Performance and Enhanced Parasitic Mitigation by Low-Temperature Batch Fabrication

This study investigates a hybrid microelectromechanical system (MEMS) acoustic resonator through a hybrid approach to combine capacitive and piezoelectric transduction mechanisms, thus harnessing the advantages of both transducer technologies within a single device. By seamlessly integrating both piezoelectric and capacitive transducers, the newly designed hybrid resonators mitigate the limitations of capacitive and piezoelectric resonators. The unique hybrid configuration holds promise to significantly enhance overall device performance, particularly in terms of quality factor (Q-factor), insertion loss, and motional impedance. Moreover, the dual-transduction approach improves the signal-to-noise ratio and reduces feedthrough noise levels at higher frequencies. In this paper, the detailed design, complex fabrication processes, and thorough experimental validation are presented, demonstrating substantial performance enhancement potentials. A hybrid disk resonator with a single side-supporting anchor achieved an outstanding loaded Q-factor higher than 28,000 when operating under a capacitive drive and piezoelectric sense configuration. This is comparably higher than the measured Q-factor of 7600 for another disk resonator with two side-supporting anchors. The hybrid resonator exhibits a high Q-factor at its resonance frequency at 20 MHz, representing 2-fold improvement over the highest reported Q-factor for similar MEMS resonators in the literature. Also, the dual-transduction approach resulted in a more than 30 dB improvement in feedthrough suppression for devices with a 500 nm-thick ZnO layer, while hybrid resonators with a thicker piezoelectric layer of 1300 nm realized an even greater feedthrough suppression of more than 50 dB. The hybrid resonator integration strategy discussed offers an innovative solution for current and future advanced RF front-end applications, providing a versatile platform for future innovations in on-chip resonator technology. This work has the potential to lead to advancements in MEMS resonator technology, facilitating some significant improvements in multi-frequency and frequency agile RF applications through the original designs equipped with integrated capacitive and piezoelectric transduction mechanisms. The hybrid design also results in remarkable performance metrics, making it an ideal candidate for integrating next-generation wireless communication devices where size, cost, and energy efficiency are critical.

Temperature Effects in Packaged RF MEMS Switches with Optimized Gold Electroplating Process.

Due to its excellent electrical performance, mechanical reliability, and thermal stability, electroplated gold is still the most commonly used material for movable beams in RF MEMS switches. This paper investigates the influence of process conditions on the quality and growth rate of gold electroplating, and the optimized process parameters for the gold electroplating process are obtained. The characterization of the optimized electroplated gold layer shows that it has small surface roughness and excellent thermal stability. With this optimized gold electroplating process, the RF MEMS switches are fabricated and hermetic packaged. In order to obtain the temperature environment adaptability of the packaged switch, the influence of working temperature is studied. The temperature effects on mechanical performance (includes pull-in voltage and lifetime) and RF performance (includes insertion loss and isolation) are revealed.

Hysteresis impact of ferroelectric oxide on double-source vertical tunnel FET: DC and RF performance

Hysteresis impact of ferroelectric oxide on double-source vertical tunnel FET: DC and RF performance

Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

Vertical Interconnection Technology for RF MicroSystem Packaging.

In this work, 1.5-level interconnections of RF microsystems with good RF performance, integration process compatibility, and high reliability are developed to meet the future demand for wireless communication microsystems in the millimeter wave band. Numerical models of 1.5-level interconnections based on solder balls with different diameters are established and analyzed using HFSS. The optimized structure parameters of 0.2 mm diameter Sn96.5Ag3Cu0.5 (SAC305) solder balls and 0.3 mm diameter Sn63Pb37 solder balls are selected for the interconnection between glass micro substrates and silicon micro substrates and between silicon micro substrates and HTCC substrates, respectively. Integration process parameters of the vertical interconnection are optimized. The micro substrate interconnection samples manufactured based on optimized integration methods and parameters show high reliability.

InAlGaN-based HEMT with very low Ohmic contact resistance regrown at 850 °C by MOVPE

Regrown Ohmic contacts have been widely studied for high millimeter-wave applications. However, few were applied to InAl(Ga)N-based HEMT despite the lattice match benefits with GaN channel because of the poor thermal stability of the quaternary barrier. In this article, we use relatively low temperature (850 °C) MOVPE technique for the regrowth of heavily Si doped GaN (1 × 1020 cm−3) to avoid deterioration of the channel's electrical characteristics. Moreover, high selectivity of the regrowth is obtained, thanks to large opening ratio of the hard mask. The state-of-the-art total Ohmic contact resistance Rc = 0.06 Ω mm is reached with high homogeneity on a 4-in. wafer. This result reflects the combined contribution of the doped GaN interfaces with both the metal contact and the channel. 2 × 50 μm transistors featuring 100 nm gate length with regrown Ohmic contacts present remarkable improvements of DC and RF performances. At 40 GHz, the highest Power Added Efficiency (PAE) of 54% is attained at an output power of 3.8 W mm−1, while the maximum output power of 9.4 W mm−1 is achieved at a PAE of 48%, corresponding to bias voltages of 15 and 30 V, respectively.

Comprehensive characterization of a high‐performance double heterojunction InGaAs pHEMT for linear power‐efficient amplifiers applications

AbstractThis article centers its attention on the phenomenon of electrostatics, linearity, analogue, and RF performance of a 0.5 μm × (2 × 100) μm double heterojunction AlGaAs/InGaAs/GaAs pHEMT using on‐wafer DC and RF measurements up to 50 GHz. With a high ION/IOFF ratio (1.21 × 107) and low subthreshold slope (72.7 mV/dec), a flat and high transconductance over a wide range of Vgs has been achieved for the tested device. Furthermore, the input intercept and higher‐order voltage intercept point both attained large values with low intermodulation and harmonic distortion. Regarding RF parameters, the intrinsic gain has been achieved up to 28 dB. The GBW up to 750 GHz was attained, with the highest fT and fmax values being 24.5 GHz and 99.3 GHz, respectively. Since the device has very low intrinsic capacitance, parameters like TFP, GFP, and GTFP also showed excellent results. The high intrinsic gain and TGF indicate ample potential of the device for use as an amplifier. Investigating the parameters reveals the device to have very good linearity and amplifying capability.

Development of a 166.6MHz β = 1 higher-order-mode-damped superconducting cavity.

The storage ring of the high energy photon source will be driven by five 166.6MHz β = 1 quarter-wave superconducting cavities operating at 4K. A higher-order-mode-damped superconducting cavity was designed with excellent rf and mechanical properties based on the successful development of the proof-of-principle cavity. The mechanical design of the dressed cavity was focused on addressing stress safety throughout the processes, tunability, frequency detuning due to pressure fluctuation, and Lorentz force, among other factors. A new liquid helium vessel was designed along with a comprehensive stiffening scheme to mitigate the surging peak stress on the cavity resulting from the significantly unequal beam pipe size. In the first batch, three cavities were manufactured, and surface preparations were carefully conducted to eliminate defects and etching traces while ensuring cleanliness. The cavity's Q0 at the design voltage of 1.5 MV reached 3.8 × 109 at 4K, comfortably surpassing the design goal. Field emission onset was not observed during the entire test up to a peak electric field of 60 MV/m, thanks to the optimized processing procedures. Subsequently, one cavity was welded with the newly designed helium vessel and vertically tested at 2K, achieving an rf performance comparable to the bare cavities, demonstrating the success of the jacketed cavity. This paper presents the design, fabrication, surface preparation, and cryogenic tests of the first higher-order-mode-damped 166.6MHz β = 1 superconducting cavity.

Synergistic Effect of Ferroelectric and HfO2/SiO2 Hetero dielectrics in Junctionless FET for Analog and RF Applications

AbstractThe synergistic effect of ferroelectric and HfO2/SiO2 (Hafnium dioxide/ Silicon dioxide) hetero dielectrics in double gate Junctionless Field Effect Transistor is investigated using TCAD Tool. The study encompasses a wide range of parameters, allowing for a detailed examination of the impact of hysteresis on the overall functionality of the double gate Junctionless FET. One crucial aspect of the investigation involves examining the analog and RF performance of the device. The high transconductance (gm) of 5.42 mS, a gain of 95 dB (decibel), a cut‐off frequency of 553.9 GHz (gigahertz), a gain transconductance frequency product (GTFP) of 50.9 THz (terahertz), and a gain bandwidth product (GBW) of 188 GHz shows its great potential for analog and RF signal processing applications as well as for other high data rate wireless applications such as Machine Learning (ML), Artificial Intelligence (AI) and Internet‐of‐Thing (IoT). The low transit time of 17 ns (nano second), with high ION/IOFF ratio range of 107 shows that the device has good switching behavior also. This aspect of the research aims to unveil the device's viability for analog and high‐frequency applications, contributing valuable insights to the emerging electronic technologies field.

Impact of varying channel length on Analog/RF performances in a novel n-type silicon-based DG-JLT

Shrinking MOSFETs suffer performance hits due to short-channel effects and leakage. Junctionless transistors JLTs emerge as promising alternatives due to simpler fabrication and better gate control. This paper investigates the analog and RF performance characteristics of n-type Silicon-Based Double Gate Junctionless Transistors with varying channel lengths (15 nm, 20 nm, and 25 nm) This study evaluates analog device performance through critical parameters: drain current density (Id), transconductance (gm), output resistance (RO), intrinsic gain (gmRO), and transconductance generation factor (gm/Id). These parameters assess current handling, gain characteristics, and design efficiency, providing a comprehensive analysis for analog circuit applications. Results indicate that the device having 15 nm channel length exhibits a transconductance which is 25.38 % more than the 20 nm variant and drain current which is 44.7 % more than the latter, suggesting its superior performance to devices with longer channel lengths. In addition, the RF performance of the devices is evaluated using the small signal model of the device. This work further investigates the high-frequency response of the devices using key figures of merit (FoMs): gate capacitances (Cgs, Cgd, Cgg), cut-off frequency (fT), and maximum oscillation frequency (fMAX). These parameters quantify the influence of parasitic capacitances on switching speed and the maximum useable frequency for analog and RF applications. Analyzing Cgs, Cgd, and Cgg reveals the impact of gate control on high-frequency operation. The device having 15 nm channel length, exhibits an increase of 47.29 % in fT and 68.97 % increase in fMAX compared to device having 20 nm channel length. The findings underscore the significance of channel length optimization in enhancing the Analog and RF performance of n-type Silicon-based Double Gate Junctionless Transistors.

Field, frequency, and temperature dependencies of the surface resistance of nitrogen diffused niobium superconducting radio frequency cavities

We investigate the rf performance of several single-cell superconducting radio-frequency cavities subjected to low temperature heat treatment in nitrogen environment. The cavities were treated at temperature 120–165 °C for an extended period of time (24–48 h) either in high vacuum or in a low partial pressure of ultrapure nitrogen. The improvement in Q0 with a Q rise was observed when nitrogen gas was injected at ∼300 °C during the cavity cooldown from 800 °C and held at 165 °C, without any degradation in accelerating gradient over the baseline performance. The treatment was applied to several elliptical cavities with frequency ranging from 0.75 to 3.0 GHz, showing an improved quality factor as a result of low temperature nitrogen treatments. The Q rise feature is similar to that achieved by nitrogen alloying Nb cavities at higher temperature, followed by material removal by electropolishing. The surface modification was confirmed by the change in electronic mean free path and tuned with the temperature and duration of heat treatment. The decrease of the temperature-dependent surface resistance with increasing rf field, resulting in a Q rise, becomes stronger with increasing frequency and decreasing temperature. The data suggest a crossover frequency of ∼0.95 GHz above that the Q rise phenomenon occurs at 2 K. Some of these results can be explained qualitatively with an existing model of intrinsic field-dependence of the surface resistance with both equilibrium and nonequilibrium quasiparticle distribution functions. The change in the Q slope below 0.95 GHz may result from masking contribution of trapped magnetic flux to the residual surface resistance. Published by the American Physical Society 2024

DC and RF performance analysis of enhancement mode fin-shaped tri-gate AlGaN/GaN HEMT and MOSHEMT with ultra-thin barrier layer

The DC and RF assessment of critical barrier-AlGaN/GaN nano channel tri-gate fin-shaped High Electron Mobility Transistor (FinHEMT) is investigated for Enhancement-mode (E-mode) operation. We propose and analyze critical barrier layer (CBL) and critical-strained barrier layer (CSBL) FinHEMT for a fixed fin-shaped channel width (W fin = 160 nm) and height (H fin = 70 nm). The CBL FinHEMT ensures an E-mode operation by depleting two-dimensional electron gas (2DEG) near the channel region between AlGaN and GaN hetero-junction. The extracted threshold voltage (V T ) in CBL FinHEMT is 0.4 V as compared to −0.2 V obtained in CSBL FinHEMT. However, increased gate leakage current density and poor gate voltage swing in CBL FinHEMT is improved through a metal-oxide-semiconductor FinHEMT (FinMOSHEMT) structure by the incorporation of Al2O3 gate oxide layer between the tri-gate and CBL AlGaN layer. It results in a stable positive VT of 0.5 V due to the negatively charged Al2O3/barrier interface fixed charge density ( NAl2O3 ). The proposed CBL FinMOSHEMT has also been studied for different atomic layer deposition Al2O3 process-dependent variations in NAl2O3. The maximum on-state drain current and transconductance of 1.01 A mm−1 and 430 mS/mm have been extracted respectively with NAl2O3 of −9.2 × 1012 cm−2. Further, the RF analysis of the proposed CBL FinMOSHEMT structure with the same dimension exhibits improved f T and f max responses with 27 GHz and 90 GHz respectively over CBL FinHEMT. The results of the frequency responses obtained for the proposed design make it suitable for power electronics applications.