RF Noise Parameters Research Articles

RF noise modeling of Black Phosphorus Junctionless Trench MOSFET in strong inversion region

In this paper, RF noise modeling of Black Phosphorus Junctionless Trench (BP-JL-T) MOSFET has been investigated in strong inversion region. The simulated and modeled results are simultaneously compared with Conventional Trench (CT) MOSFET at THz frequency range. By using analytical expressions from RF equivalent schematic, few RF figure-of-merits (FOMs) have been evaluated. It is found that RF noise parameters such as noise resistance (Rn), minimum noise figure (NFmin), optimum source susceptance (Bopt) and conductance (Gopt) are reduced to more than 200%. Modeled results reveal that BP-JL-T-MOSFET minimizes RF noise thus, providing the detailed insight to RF engineers for microwave applications/RFIC design.

Layout Effects on High Frequency and Noise Parameters in MOSFETs

<p>This study reviews related studies on the impact of the layout dependent effects on high frequency and RF noise parameter performances, carried out over the past decade. It specifically focuses on the doughnut and multi- finger layouts. The doughnut style involves the polygonal and the 4- sided techniques, while the multi-finger involving the narrow-oxide diffusion (OD) and multi-OD. The polygonal versus 4-sided doughnut, and the narrow-OD with multi-fingers versus multi-OD with multi- fingers are reviewed in this study. The high frequency parameters, which are of concern in this study, are the cut- off frequency (f<sub>T</sub>) and the maximum frequency (f<sub>MAX</sub>), whereas the noise parameters involved are noise resistance (R<sub>N</sub>) and the minimum noise figure (NF<sub>min</sub>). In addition, MOSFET parameters, which are affected by the layout style that in turn may contribute to the changes in these high frequency, and noise parameters are also detailed. Such parameters include transconductance (G<sub>m</sub>); gate resistance (R<sub>g</sub>); effective mobility (μ<sub>eff</sub>); and parasitic capacitances (c<sub>gg</sub> and c<sub>gd</sub>). Investigation by others has revealed that the polygonal doughnut may have a larger total area in comparison with the 4- sided doughnut. It is also found by means of this review that the multi-finger layout style with narrow-OD and high number of fingers may have the best performance in f<sub>T</sub> and f<sub>MAX</sub>, owing partly to the improvement in G<sub>m</sub>, μ<sub>eff</sub>, c<sub>gg</sub>, c<sub>gd</sub> and low frequency noise (LFN). A multi-OD with a lower number of fingers may lead to a lower performance in f<sub>T</sub> due to a lower G<sub>m</sub>. Upon comparing the doughnut and the multi-finger layout styles, the doughnuts appeared to perform better than a standard multi-finger layout for f<sub>T</sub>, f<sub>MAX</sub>, G<sub>m</sub> and μ<sub>eff</sub> but are poorer in terms of LFN. It can then be concluded that the narrow-OD multi-finger may cause the increase of c<sub>gg</sub> as the transistor becomes narrower, whereas a multi-OD multi-finger may have high R<sub>g</sub> and therefore may lead to the increase of f<sub>T</sub> and f<sub>MAX</sub> as the transistor becomes narrower. Besides, the doughnut layout style has a higher G<sub>m</sub> and f<sub>T</sub>, leading to larger μ<sub>eff</sub> from the elimination of shallow trench isolation (STI) stress.</p>

Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs

The impact of narrow-width effects on high-frequency performance like fT, fMAX, and RF noise parameters, such as NFmin and Rn, in sub-40-nm multifinger CMOS devices is investigated in this paper. Narrow-oxide-diffusion (OD) MOSFET with smaller finger width and larger finger number can achieve lower Rg and higher fMAX. However, these narrow-OD devices suffer fT degradation and higher NFmin, even with the advantage of lower Rg. The mechanisms responsible for the tradeoff between different parameters will be presented to provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology.

Modeling the input non-quasi-static effect in small signal equivalent circuit based on charge partitioning for bipolar transistors and its impact on RF noise modeling

This paper models the input non-quasi-static (NQS) effect of bipolar transistors using charge partitioning. The input NQS effect associated with the base minority carrier transport is modeled with a RC network, while the input NQS effect associated with the base-collector space charge region (CB SCR) carrier transport is modeled with a RLC network. With the proposed input NQS equivalent circuit model, Y-parameters and RF noise parameters using the van Vliet model are successfully modeled for frequencies up to f T . The transport noise model is extended to represent the van Vliet model by using two noise related time constants, which eliminates the need of Y-parameter in the description of the noise source. The input NQS effect for such model is verified to be important only for frequencies above f T /3. Analytical Y-parameter and noise solutions of a 1-D bipolar transistor at low injection level are used for validation.

Effect of High Frequency Noise Current Sources on Noise Figure for Sub-50 nm Node MOSFETs

The downscaling of CMOS technology has resulted in strong improvement in RF performance of bulk and SOI MOSFETs. In order to realize a low-noise RF circuit, a deeper understanding of the noise performance for MOSFETs is required. Thermal noise is the main noise source of the CMOS device for high frequency performance, and is dominated by the drain channel noise, induced gate noise, and their correlation noise. In this work, we measured the RF noise parameter (Fmin, Rn, Γopt) of 45nm node MOSFETs from 5 to 15GHz and extracted noise sources and noise coefficients P, R, and C by using an extended van der Ziel's model. We found, for the first time, that correlation coefficient C decreases from positive to negative values when the gate length is reduced continuously with the gate length of sub-100nm. We confirmed that Pucel's noise figure model, using noise coefficients P, R, and C, can be considered a good approximation even for sub-50nm MOSFETs. We also discussed a scaling effect of the noise coefficients, especially the correlation noise coefficient C on the minimum noise figure.

Gate-stack analysis for 45-nm CMOS devices from an RF perspective

Three gate stacks for the 45-nm node are analyzed from an RF perspective. The authors present an expression of the gate resistance valid for all three stacks, quantify the differences each stack has on several small-signal RF figures-of-merit and on the RF noise parameters, and demonstrate that devices with fully silicided gates will enable ultralow-power/low-noise RF applications, while the performance of transistors using multilayer gate stacks are limited by large contact resistance. Although offering better bandwidth and noise characteristics than the poly/silicide stack, the deposited metal stack will lose its advantage in devices requiring higher gate work functions than in planar bulk CMOS transistors.

Impact of downscaling and poly-gate depletion on the RF noise parameters of advanced nMOS transistors

For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RF noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling.

Noise in SiGe HBT RF Technology: Physics, Modeling, and Circuit Implications

This paper presents an overview of the physics, modeling, and circuit implications of RF broad-band noise, low-frequency noise, and oscillator phase noise in SiGe heterojunction bipolar transistor (HBT) RF technology. The ability to simultaneously achieve high cutoff frequency (f/sub T/), low base resistance (r/sub b/), and high current gain (/spl beta/) using Si processing underlies the low levels of low-frequency 1/f noise, RF noise, and phase noise of SiGe HBTs. We first examine the RF noise sources in SiGe HBTs and the RF noise parameters as a function of SiGe profile design, transistor biasing, sizing, and operating frequency, and then show a low-noise amplifier design example to bridge the gap between device and circuit level understandings. We then examine the low-frequency noise in SiGe HBTs and develop a methodology to determine the highest tolerable low-frequency 1/f noise for a given RF application. The upconversion of 1/f noise, base resistance thermal noise, and shot noises to phase noise is examined using circuit simulations, which show that the phase noise corner frequency in SiGe HBT oscillators is typically much smaller than the 1/f corner frequency measured under dc biasing. The implications of SiGe profile design, transistor sizing, biasing, and technology scaling are examined for all three types of noises.

An MOS transistor model for RF IC design valid in all regions of operation

This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic elements. A complete charge-based model of the intrinsic part is presented. The main advantage of this new charge-based model is to provide a simple and coherent description of the DC, AC, nonquasi-static (NQS), and noise behavior of the intrinsic MOS that is valid in all regions of operation. It is based on the forward and reverse charges q/sub f/ and q/sub r/ defined as the mobile charge densities, evaluated at the source and at the drain. This intrinsic model also includes a new simplified NQS model that uses a bias and frequency normalization allowing one to describe the high-order frequency behavior with only two simple functions. The extrinsic model includes all the terminal access series resistances, and particularly the gate resistance, the overlap, and junction capacitances as well as a substrate network. The latter is required to account for the signal coupling occurring at RF from the drain to the source and the bulk, through the junction capacitances. The noise model is then presented, including the effect of the substrate resistances on the RF noise parameters. All the aspects of the model are validated for a 0.25-/spl mu/m CMOS process.

A unified approach to RF and microwave noise parameter modeling in bipolar transistors

A unified approach to RF and microwave noise parameter modeling in bipolar transistors is presented. Circuit level noise parameters including the minimum noise figure, the optimum generator admittance, and the noise resistance are analytically linked to the fundamental noise sources and the y-parameters of the transistor through circuit analysis of the chain noisy two-port representation. Comparisons of circuit level noise parameters from different physical models of noise sources in the transistor were made against measurements in UHV/CVD SiGe HBTs. A new model for the collector shot noise is then proposed which produces better noise parameter agreement with measured data than the SPICE noise model and the thermodynamic noise model, the two most recent Y-parameter based noise models.

Direct extraction of the channel thermal noise in metal-oxide-semiconductor field effect transistor from measurements of their rf noise parameters

This article presents an extraction method to obtain the channel thermal noise in metal-oxide-semiconductor field effect transistor (MOSFETs) directly from the dc, scattering parameter and rf noise measurements. In this extraction method, the transconductance (gm), output resistance (RDS), and source and drain resistances (RS and RD) are obtained from dc measurements. The gate resistance (RG) is extracted from scattering-parameter measurements, and the equivalent noise resistance (Rn) is obtained from rf noise measurements. This method has been verified by using the measured data of a 0.36 μm n-type MOSFET up to 18 GHz. Comparisons between simulated and measured characteristics of noise parameters versus frequency are also presented.

HBT's RF noise parameter determination by means of an efficient method based on noise analysis of linear amplifier networks

A method for the evaluation of the RF noise figure of heterojunction bipolar transistors (HBTs) is presented. The noise analysis is based on the use of the correlation matrices. The two-port device is described as an interconnection of basic two-port devices whose noise behaviour is known. The circuit theory of linear noisy networks allows that any two-port device can be replaced by a noise equivalent circuit which consists of the original two-port assumed to be noiseless and possess two additional noise sources. The purpose of this paper is to obtain the four noise parameters of the device, taking into account the excess resistances and inductances. The calculations presented show good agreement with measurements, and as a consequence, they permit a good estimation of the noise performance of the structure without neglecting any parasitic elements of the equivalent circuit.