RF Front-end Design Research Articles

A Switchless, $Q$-Band Bidirectional Transceiver in 0.12-$\mu$m SiGe BiCMOS Technology

A fully-integrated Q-band (40-45 GHz) bidirectional transceiver is demonstrated in a 0.12-μm SiGe BiCMOS technology. The RF front-end design eliminates the need for transmit/receive switches by demonstrating a novel PA/LNA circuit. The transceiver has a transmit conversion gain of 35 dB with a 3-dB bandwidth of 4 GHz. The OP1dB is 8.5 dBm and Psat is 9.5 dBm. The transceiver has a receive conversion gain of 34 dB with a 3-dB bandwidth of 3 GHz. The noise figure is 4.7 dB and OP1dB is - 5 dBm at 43 GHz. The chip consumes 119.4 mW when transmitting and 54 mW when receiving, and overall chip size is 1.6 mm × 0.8 mm including pads. To the author's knowledge, this work represents the first switchless millimeter-wave bidirectional transceiver in a CMOS or BiCMOS process.

A Subthreshold CMOS RF Front-End Design for Low-Power Band-III T-DMB/DAB Receivers

This letter presents a CMOS RF front-end operating in a subthreshold region for low-power Band-III mobile TV applications. The performance and feasibility of the RF front-end are verified by integrating with a low-IF RF tuner fabricated in a 0.13-μm CMOS technology. The RF front-end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front-end is 13.8 mW from a 1.2 V supply.

Single RF front-end MIMO transceivers

The main limitation of using multiple antenna architecture is the complexity and high cost of the hardware in the RF section. One solution to reduce the extra hardware cost and RF circuit imperfection is the utilization of a single RF front-end in a MIMO system. This article discusses the different alternatives to realize single RF front-end transceivers, including the antenna selection technique, time-division multiplexing, code-division multiplexing, and the parasitic antenna method. The implementation technique for each approach is presented, and a performance study has been conducted. The practical limitations of a single RF front-end design alternative are also discussed.

On the RF Properties of Weakly Saturated SiGe HBTs and Their Potential Use in Ultralow-Voltage Circuits

We investigate, for the first time, the feasibility of operating silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in a weakly saturated bias regime to enable ultralow-voltage RF front-end design. Measured dc, ac, and RF characteristics of third-generation high-performance SiGe HBTs operating in weak saturation are presented. Robust RF operation of 0.12 × 6.0 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SiGe HBTs are demonstrated in a common-emitter configuration at collector-to-emitter voltages above 0.15 V. A noise figure of 1.33 dB and an input third-order intercept point above -8 dBm for a 3-GHz input tone are achieved at 0.30 V. These results have potential implications for RF circuits used in severely power-constrained systems.

Silicon on insulator MESFETs for RF amplifiers

CMOS compatible, high voltage SOI MESFETs have been fabricated using a standard 3.3V CMOS process without any changes to the process flow. A 0.6μm gate length device operates with a cut-off frequency of 7.3GHz and a maximum oscillation frequency of 21GHz. There is no degradation in device performance up to its breakdown voltage, which greatly exceeds that of CMOS devices on the same process. Other figures of merit of relevance to RF front-end design are presented, including the maximum stable gain and noise figure. An accurate representation of the device in SPICE has been developed using the commercially available TOM3 model. Using the SOI MESFET model, a source degenerated low noise RF amplifier targeting operation near 1GHz has been designed. The amplifier was fabricated on a PCB board and operates at 940MHz with a minimum NF of 3.8dB and RF gain of 9.9dB while only consuming 5mW of DC power.

System considerations and RF front-end design for integration of satellite navigation and mobile standards

Abstract. The paper presents the challenges involved in a system design of a robust reconfigurable RF front-end for navigation and mobile standards. Receiver architecture is chosen from the point of view of inter-system interference and 130nm CMOS process characteristics. System concept covers the implementation of GPS, Galileo, UMTS, GSM and CDMA2000 using a Zero-IF architecture with reconfigurable analog and digital path. Feasibility studies of the system cover analysis of the wireless regulations and performance criteria, such as overall gain, noise figure (NF), and 1dB compression point (P1dB) of the RF chain, phase noise requirements and VCO tuning range [1]. The presented chip was fabricated in 130 nm CMOS technology. System considerations are confirmed with the chip measurements of gain, noise figure, and linearity. Prospects for the future work are presented including technology shrink.

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS

As CMOS scales down and grows more expensive, area-aware RF front-end design becomes appropriate. A wideband front-end is presented that uses an inductorless LNA and downconversion section up to 6 GHz. Frequency synthesis is realized using a single-inductor dual-band 3.5 and -10 GHz VCO. In-depth analysis describes the operation of the 4-port oscillator, and compares phase noise to that of a classical VCO. The front-end is realized in 90 nm digital CMOS. The LNA achieves a noise figure of 2.7 dB with an average IIP3 of -2 dBm. The dual-band VCO achieves a phase noise of -122 dBc/Hz and -128 dBc/Hz at 3.9 GHz and 10 GHz, respectively, at 2.5 MHz offset. Both circuits are embedded in a wideband direct-conversion front-end consuming less than 60 mW from a 1.2 V supply.

Broadband Active Receiving Patch With Resistive Equalization

The active integrated antenna (AIA) concept has been applied to design a broadband receiver front-end. A design procedure for active broadband patch antennas based on resistive equalization is presented. The use of the AIA has allowed the design of efficient RF front-ends by increasing its effective gain, noise figure, and merit . In addition to improving the classical parameters, the resistive equalization technique allows enlarging the bandwidths of the active antenna parameters versus the corresponding ones in passive antennas. A receiving patch antenna (with one amplifying stage) with a measured noise figure lower than 0.6 dB in a bandwidth over 38% and an effective gain improvement of 13 dB over the corresponding passive antenna has been achieved. The -parameter has also been measured for both the active and passive antenna, resulting in a relative planar of 16 dB/K, with a ripple of 0.5 dB, over a 30% bandwidth for the active antenna versus a of 22 dB/K for a typical front-end with a passive antenna over 20% bandwidth.

Active Integrated Antenna Design Using a Contact-Less, Proximity Coupled, Differentially Fed Technique

A novel contact-less, differential feeding technique suitable for integrated active antenna design is demonstrated. This technique utilizes an odd mode signal to generate fringing fields on either side of a microstrip gap under the antenna. This allows electromagnetic energy to be efficiently coupled from the transmission lines to the radiating antenna. In a balanced integrated antenna amplifier configuration, the proposed non-contact feeding method removes the need for any balun or power combining network. Hence in theory, a compact RF front-end design with lower losses can be realized. This feeding method has been successfully applied to the design of simple passive microstrip patch antennas and active integrated antennas (AIA). Simulated and measured results are also included to validate the proposed feeding concept and antenna designs. The performance of the proposed differential feeding technique on a simple microstrip patch antenna has been systematically studied. The study suggests that the proposed proximity method is broadband in nature, allowing antennas operating at different resonant frequencies to be swapped without the need to change the feed dimensions and without degrading the matching performance

A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications

A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1% packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip is implemented in a standard 0.18-mum CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port

Design of reconfigurable RF front-end for multi-standard receiver using switchable passive networks

For successful implementation of a multi-standard receiver, a reconfigurable receiver architecture and a reconfigurable component design technique are essential. In this paper, an adaptable receiver architecture and a reconfigurable RF design technique using a switchable passive network are proposed. To verify the proposed design technique, the reconfigurable mixer and QVCO are designed using a flexible matching network and flexible LC tank, respectively. The measurement results of each component well prove the usefulness of the switchable passive network.

Design and practical implementation of multifrequency RF front ends using direct RF sampling

The use of direct RF sampling has been explored as a means of designing multifrequency RF front ends. Such front ends will be useful to multifrequency RF applications such as global navigation satellite system receivers that use global positioning system (GPS) L1, L2, and L5 signals and Galileo signals. The design of a practical multifrequency direct RF sampling front end is dependent on having an analog-to-digital converter whose input bandwidth accommodates the highest carrier frequency and whose maximum sampling frequency is more than twice the cumulative bandwidth about the multiple carrier signals. The principle of direct RF sampling is used to alias all frequency bands of interest onto portions of the Nyquist bandwidth that do not overlap. This paper presents a new algorithm that finds the minimum sampling frequency that avoids overlap. This design approach requires a multifrequency bandpass filter for the frequency bands of interest. A prototype front end has been designed, built, and tested. It receives a GPS coarse/acquisition code at the L1 frequency and GPS antispoofing precision code at both L1 and L2. Dual-frequency signals with received carrier-to-noise ratios in excess of 52 dB-Hz have been acquired and tracked using this system.

RF integrated systems

This article will detail the advantages and the draw back of the monochip approach for the system integration, the process selection (CMOS or BiCMOS), and the needed knowledge to perform a successful design. A BiCMOS monochip, RF to digital base band on DCS1800 standard will be presented. This circuit has been designed in order to underline the substrate coupling effects. Linked to this design, a substrate coupling study will be developed. A low cost CMOS zero IF Bluetooth RF front end design will be detailed, this approach is defined in order to integrate the global RF and Base Band functions in a monochip.