RF DAC Research Articles

Analyzing the phase and amplitude noise of RZ, NRZ and RF DACs

This article considers a multi-mode RF DACs phase and amplitude noise for non-return-to-zero (NRZ), return-to-zero (RZ), and mix/RF reconstruction waveforms under the assumption that two switch pairs (or two channels) in each current switch cells are alternately active in every clock cycle, Analysis shows that each channel of multimode DAC is completely characterized with RZ mode, and all other modes can be derived from this mode, in particular NRZ mode is not a complete analog of conventional DAC performance when reconstruction pulse duration and period are equal. When determining phase and amplitude noise of multi-mode RF DAC, one should keep in mind the phase shift between two switch pairs output pulses spectral components in NRZ and RF modes. This phase shift depends upon DAC mode (NRZ or RF) and output oscillation frequency. As consequence an analysis indicates that the 3 dB improvement of 1/F phase noise can be achieved in 1st Nyquist zone when using NRZ mode, the same in 2nd Nyquist zone with RF mode if amplitude noise of DAC switch pairs is negligible. The independence of 1/F noise from clock frequency has simple physical interpretation. As correlation period of 1/F noise is significantly greater than output oscillation period, the delay of this oscillation caused by phase fluctuations in DAC is the same for any mode, and analysis of noise spectral density for conventional DAC can be extended to multi-mode RF DACs.

Relation Between INL and ACPR of RF DACs

The integral nonlinearity of digital-to-analog converters manifests itself as adjacent-channel power in RF transmitters. This paper derives compact equations relating these two quantities and verifies the results by simulations. Both current-steering and switched-mode architectures are analyzed.

A 6-GHz MU-MIMO Eight-Element Direct Digital Beamforming TX Utilizing FIR H-Bridge DAC

Targeting the next generation of Wi-Fi (WiFi-6E), this work extends the bandwidth and frequency range of digital-phase-shifting direct-digital-to-RF TX, paving the way for use in high-speed multiuser, multiple-input-multiple-output (MU-MIMO) wireless systems. Careful frequency planning and a mostly digital upconversion scheme facilitate digital automation. Digital delta-sigma modulation enables an inherently linear 1b RF DAC. Low-loss digital filtering suppresses delta-sigma DAC noise and mitigates the challenges of filtering a 6-GHz RF frequency. An H-bridge combines current-DAC, finite-impulse response (FIR) filtering, and RF upconversion. A 28-nm CMOS eight-element 6-GHz beamforming TX prototype has a per-element area of 0.01 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a per-element power consumption of 47.5 mW.

High-Fidelity Control of Superconducting Qubits Using Direct Microwave Synthesis in Higher Nyquist Zones

Control electronics for superconducting quantum processors have strict requirements for accurate command of the sensitive quantum states of their qubits. Hinging on the purity of ultra-phase-stable oscillators to upconvert very-low-noise baseband pulses, conventional control systems can become prohibitively complex and expensive when scaling to larger quantum devices, especially as high sampling rates become desirable for fine-grained pulse shaping. Few-GHz radio-frequency digital-to-analog converters (RF DACs) present a more economical avenue for high-fidelity control while simultaneously providing greater command over the spectrum of the synthesized signal. Modern RF DACs with extra-wide bandwidths are able to directly synthesize tones above their sampling rates, thereby keeping the system clock rate at a level compatible with modern digital logic systems while still being able to generate high-frequency pulses with arbitrary profiles. We have incorporated custom superconducting qubit control logic into off-the-shelf hardware capable of low-noise pulse synthesis up to 7.5 GHz using an RF DAC clocked at 5 GHz. Our approach enables highly linear and stable microwave synthesis over a wide bandwidth, giving rise to high-resolution control and a reduced number of required signal sources per qubit. We characterize the performance of the hardware using a five-transmon superconducting device and demonstrate consistently reduced two-qubit gate error (as low as 1.8%) which we show results from superior control chain linearity compared to traditional configurations. The exceptional flexibility and stability further establish a foundation for scalable quantum control beyond intermediate-scale devices.

Digital Evolution of the Quadrature Balanced Power Amplifier Transceiver for Full Duplex Wireless Operation

This letter compares analog and digital implementations of quadrature balanced power amplifier (QBPA) transceiver for full-duplex wireless operation. The design considerations of both architectures are laid out, and a comprehensive performance comparison between the two approaches based on theoretical and experimental results is proposed. For this end, a new QBPA chip prototype employing voltage-mode switched-capacitor RF DACs was fabricated in TSMC’s 65 nm CMOS, whereas the analog QBPA, reported in our previous work, comprises 180 nm CMOS current-mode class-AB PAs. We demonstrate that while both techniques can achieve deep interference cancellation, the switched-capacitor QBPA (SC-QBPA) exhibits considerably better performance in terms of noise figure (NF), linearity, and system efficiency. At 8 dB backoff from 20 dBm peak TX power, the SC-QBPA achieves 17 dB improvement in NF and 10 dB better linearity. The analog QBPA, on the other hand, can reach higher operating frequencies and has 1.4 dB lower RX insertion loss.

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radio’s digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into today’s digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital ΣΔ modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

Design, Realization, and Evaluation of a Riemann Pump in GaN Technology

The realization of a novel Riemann Pump for radio frequency digital-to-analog converters (RF DACs) in combination with a power amplifier is presented, which improves the signal-to-noise ratio of conventional converter concepts. The presented concept results in an arbitrary waveform generator that at the same time is capable to provide several watts of output power at RF-frequencies to $50~\Omega $ . Furthermore, the gallium nitride (GaN) high-electron-mobility transistor technology provides high-switching frequencies to ensure an oversampling ratio of 5 for a wide baseband bandwidth. The Riemann Pump, which is controlled with a digital bit-stream, is based on the current-steering topology and provides the possibility to synthesize arbitrary waveforms. A 2-b RF DAC was designed with multiple GaN monolithic microwave-integrated circuits and proves the feasibility to generate arbitrary waveforms. Measurement results yield triangular signals with a baseband frequency of 100 MHz for an input-control data rate of 200 Mb/s.

A Nonlinear Switched State-Space Model for Capacitive RF DACs

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements.

A Class-G Switched-Capacitor RF Power Amplifier

A switched-capacitor power amplifier (SCPA) that realizes an envelope elimination and restoration/polar class-G topology is introduced. A novel voltage-tolerant switch enables the use of two power supply voltages which increases efficiency and output power simultaneously. Envelope digital-to-analog conversion in the polar transmitter is achieved using an SC RF DAC that exhibits high efficiency at typical output power backoff levels. In addition, high linearity is achieved and no digital predistortion is required. Implemented in 65 nm CMOS, the measured peak output power and power-added efficiency (PAE) are 24.3 dBm and 43.5%, respectively, whereas when amplifying 802.11g 64-QAM OFDM signals, the average output power and PAE are 16.8 dBm and 33%, respectively. The measured EVM is 2.9%.

RF digital-to-analog converters enable direct synthesis of communications signals

This article discusses the practical application of RF digital-to-analog converters to communication systems such as cable distribution, wireless communications infrastructure base stations, wireless backhaul, and other such systems. The key specifications driving the development of RF DAC technology are reviewed, as are some common radio architectures used to implement those systems. Challenges associated with the design of RF DACs are described, and some trade-offs and possible solutions are discussed. Design considerations of the package and the printed circuit board design are reviewed. Measured results of an RF DAC suitable for cable head-end transmitters are presented. The features and performance of RF DACs provide an enabling solution for software defined radio systems targeted toward multicarrier, multiband, multistandard radio transmitters.

Design of CMOS Power Amplifiers

This paper describes the key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak-to-average ratio signals. We show that most important limitations arise from the limited breakdown voltage of nanoscale CMOS devices and the large back-off requirements to achieve the required linearity, both of which result in poor average efficiency. Two fundamentally different approaches to tackle these problems are presented along with silicon prototype measurements. In the first approach, transformer power combining and bias-point optimization are used to increase the output power and linearity of the “analog” amplifier. In the second approach, a mixed-signal “digital” polar architecture is employed, wherein the amplitude modulation is formed through an RF DAC structure.

Design of Fourth‐Order Continuous‐Time Bandpass ΔΣAD Modulator for RF Sampling

AbstractThis paper presents the design of a fourth‐order continuous‐time bandpass ΔΣAD modulator for RF sampling. It employs subsampling, RF DAC, as well as digital techniques to compensate for finite Q and excess loop delay, and its loop filter uses inverter‐type OTAs; these basic techniques have been described in our previous papers. This paper validates a transistor‐level circuit design of a complete fourth‐order modulator that combines all of the above techniques, and its SPICE simulation results are as follows: the center of the signal band is 2.4 GHz, the sampling frequency is 3.2 GHz, the signal bandwidth is 2 MHz, the peak SNDR is 56 dB, the power consumption from a 1.8‐V supply voltage is 50 mW, and it uses TSMC 0.18‐µm CMOS process. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

A Linear $\Sigma$–$\Delta$ Digital IF to RF DAC Transmitter With Embedded Mixer

A noise-shaped direct digital IF to RF (DIF2RF) DAC with embedded upconverter mixer is presented. The digital IF signal is noise shaped by a bandpass Sigma-Delta modulator with 1-bit IF output followed by a semidigital finite impulse response (FIR) filter. The current mode FIR filter combines scaled values of the local oscillator (LO) signal for performing reconstruction filtering and upconversion in a single module. The DIF2RF design modulates the digital IF signal with a digital LO signal. This topology eliminates the transconductance nonlinearity of conventional mixers and is inherently linear due to single-bit digital IF input. The presented architecture reduces clock jitter sensitivity of 1-bit DACs by masking IF clock transitions with LO signals. A prototype of the DIF2RF DAC is designed and fabricated in a five-layer metal 0.25-mum digital CMOS process. The architecture can be used in low-power software-defined digital-IF transmitters. The DIF2RF DAC consumes 49 mA from a 2.5-V supply, achieving -64.7-dBc third-order intermodulation at 1.03 GHz with a spurious-free dynamic range of 72 dB in a 15-MHz bandwidth.

A Digitally Controlled Oscillator System for SAW-Less Transmitters in Cellular Handsets

A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 /spl times/ GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones.

High-Speed Continuous-Time Subsampling Bandpass AD Modulator Architecture Employing Radio Frequency DAC

This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.