Reversible Sequential Circuits Research Articles

Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design

The counters that change their transition using a clock signal are called synchronous counters. While designing a synchronous counter circuit, the power consumption and the delay are the major issues. Several synchronous counters were designed previously with the help of flip flops, but they did not provide good results. The existing synchronous counters increased power consumption and delay and decreased the speed. To overcome these issues, in this manuscript, a reversible synchronous counter is designed utilizing Multiple-Controlled Toffoli (MCT) and Multiple-Controlled Fredkin (MCF) reversible logic gates. Here, three JK flip-flop designs, such as JK1, JK2, and JK3 are designed for a reversible synchronous counter. Then JK1 and JK2 are structured by MCT. Whereas the JK3 flip-flop design is designed under MCF reversible logic gates. Coding is carried out Verilog, and then the proposed Reversible synchronous counter design (RSCD) is synthesized and implemented on FPGA using a Xilinx ISE 14.5 System generator. Here, performance metrics, such as delay, power, maximum counting rate, and total equivalent gate counts are examined. The efficiency of the proposed RSCD-MCT-MCF design attains gate counts of 23.45%, 28.94%, and 29.04% and is compared to the existing designs, such as Effective Designing of Reversible Synchronous Counters in Nanoscale (SCD-MTG), effective designing for reversible sequential circuits (SCD-3TG-4FG), designing of synchronous decimal counter utilizing reversible Toffoli–FredkinNetlist (SCD-TOF2).

Efficient techniques for fault detection and location of multiple controlled Toffoli-based reversible circuit

It is very important to detect and correct faults for ensuring the validity and reliability of these circuits. In this regard, a comparative study with related existing techniques is undertaken. Two techniques to achieve the testability of reversible circuits are introduced that have been improved in terms of quantum cost and fault coverage rate. Considering this aspect, the main focus of these techniques is on the efficient detection and location of faults with 100% accuracy. These techniques for fault detection in reversible circuit design, in addition to being able to produce the correct outputs, can also provide information for fault location that has already been done at a higher cost. Proposed approaches have been successfully tested for all types of SMGF, MMGF, PMGF, RGF, and SBF. In order to verify the functional correctness of the proposed scheme, it also has executed the testing over a reversible full adder circuit, and findings are checked. In the following, the proposed approach of reversible sequential circuits is presented for the first time so far. The cost metrics are evaluated for all the proposed designs and compared the estimated results against some existing design approaches of reversible circuits for better understanding.

Comparative Review on Efficient Design of Reversible Sequential Circuits based on Optimization Parameters

Reversible computing, a well known research area in the field of computer science. One of the aims of reversible computing is to design low power digital circuits that dissipates no energy to heat. The main challenge of designing reversible circuits is to optimize the parameters which make the design costly. In this paper, we review different designs of efficient reversible sequential circuits and prepare a comparative statement based on eight optimization parameters such as Quantum Cost (QC), Delay (del), Garbage Output (GO), Constant Input (CI), Gate Level (GL), Number of Gate (NoG), Type of Gate (ToG), Hardware Complexity (HC) of Circuit.

Efficient designs of reversible sequential circuits

Recently, the synthesis of reversible sequential circuits has attracted researchers’ attention for implementing low-power logic designs. So far, the direct and replacement techniques have been used in the reversible sequential circuits design. The replacement technique leads to high quantum cost. There is the principle to look for efficient reversible circuits composed of Clifford + T gates by optimizing quantum cost, the number of T gates, and particularly the T-depth of the circuit, which depends on the type and layout of the reversible gates used in the function. This paper has proposed an optimized version of direct feedback technique without any flip-flops and is performed on several samples of reversible circuits design, such as counters and shift registers. It has been shown that by partial changes in the direct technique, quantum cost and other cost metrics have been improved. It has also displayed some efficient designs of the reversible parallel-to-serial converter with parity capability and low-cost design of the control unit for a reversible self-controlled serial adder system. The analysis and comparison depict that all new proposed designs have optimized the existing works in terms of performance variables, including quantum cost, number of T gates, and T-depth of the circuit.

General Method to Design Reversible Universal n-Bit Up/Down Counters

With the growing trend towards reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers, and designing reversible circuits is one of the approaches proposed for reducing power consumption. Although several studies have been done in the field of synthesizing combinational reversible circuits, little work has been done for designing reversible sequential circuits. Furthermore, many researches in this context use traditional designs which replace latches, flip-flops and associated combinational gates with their reversible counterparts. This traditional technique is not very promising, because it leads to high quantum cost (QC) and garbage outputs. Recently, researchers have proposed direct design of reversible sequential circuits using Reed Muller expressions to obtain next state output. Since most sequential circuits have multiple outputs, using common product terms between multiple outputs might decrease QC significantly. In this paper, a modular and low QC design for a synchronous reversible [Formula: see text]-bit up/down counter with parallel load capability is presented. In this design, the common terms among multiple outputs are used efficiently, which leads to a low QC for the counter. A general formula to evaluate the QC of our proposed reversible counter is presented. This result shows that in our proposed design by increasing the number of bits of counter ([Formula: see text], the QC increases linearly, while in previous works by increasing the number of bits of counter, the QC increases exponentially.

Low-cost and compact design method for reversible sequential circuits

Reversible logic plays an important role in nanotechnology-based systems; therefore, it has become an interesting topic for many researchers in this field. Although many researchers are investigating techniques to synthesize reversible combinational logic, few are working in the field of reversible sequential logic. The traditional method to design a sequential circuit is a replacement technique. In this technique, in order to design a reversible sequential circuit, all parts of an irreversible design (e.g., latches and flip-flops and associated combinational gates) are replaced by their reversible counter parts, which leads to circuits with high quantum cost. In this paper, we propose a direct and compact design of reversible synchronous sequential circuits. The EXOR of Products of EXOR (EPOE) expressions are applied, to reduce the quantum cost of sequential logic circuits. We present designs for some practical sequential circuits, such as state machines, counters and shift registers. To show the efficiency of the proposed method, we have designed a proof of concept of our designs to design a practical sequential system: a reversible self-controlled serial adder. Our designs considerably reduce performance cost factors: including quantum cost, number of constant inputs or the number of garbage outputs and delay.

Design and Implementation of Multiple Input Multiple Output Reversible Sequential Circuit

Design and Implementation of Multiple Input Multiple Output Reversible Sequential Circuit

First Steps in Creating Online Testable Reversible Sequential Circuits

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops and the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving upon the replacement technique in both quantum cost and ancilla inputs. We present here a further improved version of the direct feedback method. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs. We also propose the first technique for online testing of single line faults in sequential reversible circuits.

Novel Tree Structure Based Conservative Reversible Binary Coded Decimal Adder and Sequential Circuit with Added High Testability

Novel Tree Structure Based Conservative Reversible Binary Coded Decimal Adder and Sequential Circuit with Added High Testability

Design of reversible sequential circuits using electro-optic effect of lithium-niobate-based Mach–Zehnder interferometers

In recent years, it has been shown that reversible logic can play an important role in power optimization for computer design. The various reversible logic gates such as Feynman, Fredkin, Peres, and Toffoli gates have been discussed by researchers, but very little work has been done on reversible sequential circuits. Design of reversible sequential circuits using lithium-niobate-based Mach–Zehnder interferometers is proposed. Here, flip-flops are designed with the help of basic reversible logic gates such as Feynman, Fredkin, and Peres gates. Theoretical descriptions along with mathematical formulation of the devices are provided. The devices are also analyzed through finite difference-beam propagation method and MATLAB® simulation.

Novel Designs of Quantum Reversible Counters

Reversible logic, as an interesting and important issue, has been widely used in designing combinational and sequential circuits for low-power and high-speed computation. Though a significant number of works have been done on reversible combinational logic, the realization of reversible sequential circuit is still at premature stage. Reversible counter is not only an important part of the sequential circuit but also an essential part of the quantum circuit system. In this paper, we designed two kinds of novel reversible counters. In order to construct counter, the innovative reversible T Flip-flop Gate (TFG), T Flip-flop block (T_FF) and JK flip-flop block (JK_FF) are proposed. Based on the above blocks and some existing reversible gates, the 4-bit binary-coded decimal (BCD) counter and controlled Up/Down synchronous counter are designed. With the help of Verilog hardware description language (Verilog HDL), these counters above have been modeled and confirmed. According to the simulation results, our circuits’ logic structures are validated. Compared to the existing ones in terms of quantum cost (QC), delay (DL) and garbage outputs (GBO), it can be concluded that our designs perform better than the others. There is no doubt that they can be used as a kind of important storage components to be applied in future low-power computing systems.

A Fault Analysis in Reversible Sequential Circuits

In this paper, the researchers propose the design of reversible circuits using reversible gates. Reversible logic is implemented in reversible circuits. Reversible logic is mostly preferred due to less heat dissipation. Conservative logic gates can be designed in any sequential circuits and can be tested using two test vectors. The significance of proposed work lies in the design of reversible sequential circuits and their equivalent circuits for maximum fault coverage. The design of reversible sequential circuits using Toffoli gate and Peres gate is proposed in this literature. The design of Toffoli and Peres equivalent circuits is proposed first time in this literature, in order to achieve maximum fault coverage. The proposed Toffoli and Peres gates surpass the Fredkin gate and MXCQCA gate in terms of area, number of gates and timing. The simulation and coding is performed using cadence tool. Keywords—Reversible logic, Peres gate, Toffoli gate, Feynman gate, latches.

Design of Testable Reversible Sequential Circuits

In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1's, and all 0's. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible design of the DET flip-flop is proposed for the first time in the literature. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum-dot cellular automata (QCA) layout of the Fredkin gate. We are also presenting a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area.

Quantum Cost Optimization for Reversible Sequential Circuit

Reversible sequential circuits are going to be the significant memory blocks for the forthcoming computing devices for their ultra low power consumption. Therefore design of various types of latches has been considered a major objective for the researchers quite a long time. In this paper we proposed efficient design of reversible sequential circuits that are optimized in terms of quantum cost, delay and garbage outputs. For this we proposed a new 3*3 reversible gate called SAM gate and we then design efficient sequential circuits using SAM gate along with some of the basic reversible logic gates.

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

Optically implementable designs of reversible sequential devices

We have proposed some new designs of reversible sequential circuits using NCT gate library and compared them with the earlier proposals. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. We have addressed some conceptual issues related to the feedback and the choice of gate library. Further it is shown that the proposed quantum / reversible circuits can be implemented optically.

Synthesis of reversible sequential elements

To construct a reversible sequential circuit, reversible sequential elements are required. This work presents novel designs of reversible sequential elements such as the D latch, JK latch, and T latch. Based on these reversible latches, we construct the designs of the corresponding flip-flops. Then we further discuss the physical implementations of our designs based on electron waveguide Y-branch switch technology. Test costs, including test generation and test application, of reversible sequential circuits with these reversible flip-flops are also discussed. Compared with previous work, the implementation cost of our new designs, including the number of gates and the number of garbage outputs, is significantly reduced. The number of gates in our designs is 47.4% of the designs in previous work on average. The number of garbage outputs in our designs is 25% of the designs in previous work on average.