Reversible Quantum-dot Cellular Automata Research Articles

Advancing nanoscale computing: Efficient reversible ALU in quantum-dot cellular automata

This paper presents a significant contribution to the field of nanoscale computing by proposing an innovative reversible Arithmetic and Logic Unit (ALU) implemented in Quantum-Dot Cellular Automata (QCA). Reversible logic and QCA technology offer promising alternatives to conventional CMOS technology, addressing the challenges of operating at nanoscale dimensions. The primary objective is to develop a highly efficient ALU capable of performing 26 distinct arithmetic and logical operations. The ALU design is based on a novel reversible full adder-subtractor optimized for minimal quantum cost, which is crucial for energy-efficient quantum computation. The evaluation encompasses various criteria related to reversibility, such as gate count, number of constant inputs, number of garbage outputs, and quantum cost. QCA-specific criteria, including cell count, occupied area, and clock cycles, are also considered. The outcomes of this research contribute to the advancement of cell-efficient nanoscale computing, with implications for quantum computation, emerging technologies, and future integrated circuit design.

An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature.

Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit.

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell and electrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lower power, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer's central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCADesigner-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area.

Novel ultra-energy-efficient reversible designs of sequential logic quantum-dot cellular automata flip-flop circuits

Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively.

Design and Analysis of Novel Non-Reversible & Reversible Parity Generator and Detector in Quantum Cellular Automata using Feynman Gate

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Conclusion: Using reversible logic, a fault-tolerant and defect-sensitive circuit are developed for parity generation and detection.

QCA with reversible arithmetic and logic unit for nanoelectronics applications

PurposeIn this research work, brief quantum-dot cellular automata (QCA) concepts are discussed through arithmetic and logic units. This work is most useful for nanoelectronic applications, VLSI industry mainly depends on this type of fault-tolerant QCA based arithmetic logic unit (ALU) design. The ALU design is mainly depending on set instructions and rules; these are maintained through low-power ultra-functional tricks only possible with QCA-based reversible arithmetic and logic unit for nanoelectronics. The main objective of this investigation is to design an ultra-low power and ultra-high-speed ALU design with QCA technology. The following QCA method has been implemented through reversible logic.Design/methodology/approachQCA logic is the main and critical condition for realizing NANO-scale design that delivers considerably fast integrate module, effective performable computation and is less energy efficiency at the nano-scale (QCA). Processors need an ALU in order to process and calculate data. Fault-resistant ALU in QCA technology utilizing reverse logic is the primary objective of this study. There are now two sections, i.e. reversible ALU (RAU), logical (LAU) and arithmetical (RAU).FindingsA reversible 2 × 1 multiplexer based on the Fredkin gate (FRG) was developed to allow users to choose between arithmetic and logical operations. QCA full adders are also implemented to improve arithmetic operations' performance. The ALU is built using reversible logic gates that are fault-tolerant.Originality/valueIn contrast to earlier research, the suggested reversible multilayered ALU with reversible QCA operation is imported. The 8- and 16-bit ALU, as well as logical unit functioning, is designed through fewer gates, constant inputs and outputs. This implementation is designed on the Mentor Graphics QCA tool and verifies all functionalities.

Optimized area efficient quantum dot cellular automata based reversible code converter circuits: design and energy performance estimation

Quantum-dot cellular automata (QCA) based circuit designs are creating a surge in transistorless computational technologies. Due to its quasi-adiabatic switching resulting in extremely low leakage power dissipation as there is no continuous path. These circuits also enjoy extremely high packaging density of the order of 10 $$^{12}$$ devices/ $$\hbox {cm}^2$$ because of its extremely scaled area of 18 nm x 18 nm along with very high 100 GHz frequency of operation. Further the loss of bit information could be abolished by reversible logic computing. This thereby realizes an energy efficient logic operations owing to bijective relation between inputs and outputs in reversible logic. This work investigates the code converter circuits which converts 4-bit binary code to excess-3 code and vice versa based on reversible QCA logic gates for the first time. Moreover an area efficient design for 4-bit binary to gray and vice-versa code converters also designed here. All these four code converter circuits are designed using reversible logic gate Feynman and Peres gates by deploying the QCA Designer and Designer-E tool v2.0.3. Finally the in depth performance estimation of the proposed circuits in terms of circuit complexity, quantum cost and energy dissipation are also presented here. Moreover, these QCA based circuits provide a strong evidence that reversible logic based QCA circuits can be efficiently deployed for these code converter circuits.

Fault Tolerant Reversible Gate Based Sequential Quantum Dot Cellular Automata Circuits: Design and Contemplation

In the era of quantum computing, Quantum Dot Cellular Automata (QCA) is a phenomenal technology which can produce low power, high speed and area efficient circuits. On the other hand, reversible logic is a promising paradigm which is used to construct low power circuits. This paper presents a design of a unique reversible gate based on QCA. This gate can facilitate the design of complex, cost efficient sequential circuits. The proposed gate is examined for various performance parameters such as realization of standard Boolean functions, cost function, energy dissipation and fault characterization. It is observed that the proposed gate exhibits superior performance as compared to the previously reported cost efficient designs in all the performance parameters. Furthermore, to evaluate the efficacy of the proposed QCA gate, reversible sequential latches are designed. The proposed structures of latches excel over the similar existing designs and have shown 50% improvement in latency, 58% improvement in effective cell area and around 70% improvement in cost function. The proposed latches are further investigated for temperature alterations to find the operating range of temperature for the circuits. The reversible QCA gate, proposed in this paper can be effectively used to design D latch, T latch, JK latch with improved performance. Hence, the proposed gate can find extensive scope in designing cost effective, low power, reversible sequential and combinational circuits.

Optimal Energy Efficiency and Throughput on Partially Reversible Pipelined QCA Circuits

Editor's note: The low-power aspects for Quantum-dot Cellular Automata (QCA) devices are evaluated and discussed. The optimal power and throughput tradeoff is presented in the manuscript. Especially the complex parameterization of the QCA circuit is an important topic which is discussed in the manuscript.----Michael Hübner, Brandenburg University of Technology.

Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architectures.

A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency

A novel Parity-Preserving Reversible Gate (PPRG) is developed using Quantum-dot Cellular Automata (QCA) technology. PPRG enables rich fault-tolerance features, as well as reversibility attributes sought for energy-neutral computation. Performance of the PPRG design is validated through implementing thirteen standard combinational Boolean functions of three variables, which demonstrate from 10.7 to 41.9 percent improvement over the previous gate counts obtained with other reversible and/or preserving gate designs. Switching and leakage energy dissipation as low as 0.141 eV and 0.294 eV, for 1.5 $E_k$ energy level are achieved using PPRG, respectively. The utility of PPRG is leveraged to design a one-bit full adder with 171 cells occupying only 0.19 $\mu \text{m}^2$ area. Finally, fault detection and isolation properties are formalized into a concise procedure. PPRG-based circuits capable of self-configuring active recovery for selected three-variable standard functions are realized using a memoryless method irrespective of garbage outputs.

Computational fidelity in reversible quantum-dot cellular automata channel routing under thermal randomness

The computational fidelity is the measure, which imposes the knowledge about how far any noisy computational channel resembles the accurate output for the distribution of the same input. The logical operations and signalpropagation through semiconductor quantum-dot cellular automata (QCA) having different cell’s polarization are affected with environmental noise such as thermal randomness. This paper outlines the computational fidelity in reversible QCA channel routing for noiseless, as well as noisy reversible QCA channels. To show the fidelity for reversible QCA channels, QCA based Feynman gate, Fredkin gate, Peres gate and Toffoli gate have been assumed as a reversible routing channels. Shannon’s theory has been applied to measure the fidelity, which confirms the robustness in reversible QCA channel routing. The temperature range at which reversible QCA channels yield trustworthy computation is proposed in this article. It is established that the computational fidelity of the routing channels deteriorates with thermal randomness. On an average, those routing channels have reliable fidelity when perform computation in between 1K to 10K temperatures. Hence, all the routing channels yield considerable computational fidelity over the low thermal regions. The evaluation of theoretical values through simulation results establishes the design accuracy for the proposed reversible QCA routing channels.

An optimal design of conservative efficient reversible parity logic circuits using QCA

Quantum-dot Cellular Automata (QCA) is a new nano-innovation in digital systems. It is a possible alternative to ordinary CMOS technology. It offers several advantages in reversible logic such as small size and low power dissipation. Therefore, lots of attentions have been paid to implement different reversible QCA circuits. In this way, an improved model of low power odd-parity-bit, generator and checker have been proposed based on the reversible Feynman gate. The proposed reversible odd-parity-bit, generator and checker can be used to check/detect bit loss of information in telecommunication network systems. The proposed parity generator is 57% faster and occupies 38% lesser area than the previous best design. Furthermore, the proposed Nano-communication system dissipates 65% less energy at 0.5 Ek tunneling energy level. A detailed performance evaluation and power analysis are performed in different aspects to authenticate our proposed bit preservation circuits have superb performance in comparison to previously reported works. The results of the proposed circuits have been verified using QCA Designer and the power calculations have been carried out using QCA Pro tool.

Nanocommunication network design using QCA reversible crossbar switch

Crossbar switch is an essential component in communication network like telephony and circuit switching network to process information. This paper deals with the design of reversible 2×2 crossbar switch and its realization in Quantum-Dot Cellular Automata (QCA) for the first time. The proposed switch is applied to a nanocommunication circuit and its impact on information processing is observed and explored. Several parameters like logic gates, density and latency are considered to evaluate the design which confirms faster operating speed and high device density. Proposed reversible QCA circuits are compared with similar traditional circuits in terms of circuit cost. The comparison outlines that the proposed QCA circuits are cost efficient than that of similar traditional circuits. The estimation of power dissipation shows that the proposed crossbar switch has very low power dissipation suitable for reversible computing. The stuck-at-fault effect on the crossbar switch and nanocommunication circuit is also explored.

Binary to gray and gray to binary converter in quantum-dot cellular automata

The current VLSI technology is based on CMOS technology. The recent challenges of this technology caused to proposed new technology based on quantum-dot cellular automata (QCA). Structures in this technology are based on quantum cells and their sizes are nanoscale. This feature is caused to occur faults in QCA circuits. To resolve this problem can be used testable reversible logic gates in circuits. In this paper, we propose a new two-input XOR gate. Then we describe a non-reversible QCA structure and subsequently reversible QCA structure for 4-bit binary to gray and gray to binary converter. These structures are simulated with QCADesigner and compared with previous structures.

Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU

Reversible logic is emerging as a prospective logic design style for implementing ultra-low-power VLSI circuits. It promises low-power consuming circuits by nullifying the energy dissipation in irreversible logic. On the other hand, as a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises energy efficient digital design with high device density and high computing speed. The integration of reversible logic in QCA circuit is expected to be effective in addressing the issue of energy dissipation at nano scale regime. This work targets the design of reversible ALU (arithmetic logic unit) in QCA framework and proposes a new “Reversible QCA” (RQCA). The primary design focus is on optimizing the number of reversible gates, quantum cost and the garbage outputs that are the most important hindrances in realizing reversible logic. Besides optimization, the fault coverage capability of RQCA under missing/additional cell deposition defects is analysed. The scope of reversible logic is further outstretched by introducing a novel DFT (design for testability) architecture around the reversible ALU that reduces testing overhead. The performance of proposed ALU is evaluated, subjected to different faults, and is established to be more effective than the existing ALU.

Are QCA cryptographic circuits resistant to power analysis attack?

Quantum-dot cellular automata (QCA) technology is expected to offer fast computation performance, high density, and low power consumption. Thus, researchers believe that QCA may be an attractive alternative to CMOS for future digital designs. Side channel attacks, such as power analysis attacks, have become a significant threat to the security of CMOS cryptographic circuits. A power analysis attack can reveal the secret key from measurements of the power consumption during the encryption and decryption process. As there is no electric current flow in QCA technology, the power consumption of QCA circuits is extremely low when compared to their CMOS counterparts. Therefore, in this paper an investigation into both the best and worst case scenarios for attackers is carried out to ascertain if QCA circuits are immune to power analysis attack. A QCA design of a submodule of the Serpent cipher is proposed. In comparison to a previous design, the proposed design is more efficient in terms of complexity, area, and latency. By using an upper bound power model, the first power analysis attack of a QCA cryptographic circuit is presented. The simulation results show that even though the power consumption is low, it can still be correlated with the correct key guess, and all possible subkeys applied to the Serpent submodule can be revealed in the best case scenario. Therefore, in theory QCA cryptographic circuits would be vulnerable to power analysis attack. However, the security of practical QCA devices can be greatly improved by applying a smoother clock. Moreover, in the worst case scenario, the design of logically reversible QCA circuits with Bennett clocking could be used as a natural countermeasure to power analysis attack. Therefore, it is believed that QCA could be a niche technology in the future for the implementation of security architectures resistant to power analysis attack.

Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates

Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic in array systems. Testability of 1D arrays consisting of reversible QCA gates is investigated for multiple faulty modules. It has been shown that fault masking is possible in the presence of multiple faults without additional lines for controllability and observability. A technique for achieving C-testability of a 1D array is introduced by adding lines for observability. By adding lines for controllability, as well as observability, the array may be fully tested with a smaller number of test patterns. Different cases of arrays made of QCA reversible gates are presented to illustrate the applicability of the proposed testing method.

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA

An extensive literature exists on the mathematical characterization of reversible logic. However, the possible technological basis of this computing paradigm still remains unsolved. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (referred to as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. Due to the expected high error rates in nano-scale manufacturing, testing of nano devices, including QCA, has received considerable attention. The focus of this paper is on the testability of a one-dimensional array made of QCA reversible gates, because the bijective nature of reversible gates significantly facilitates testing of arrays. The investigation of testability relies on a fault model for molecular QCA that is based on a single missing/additional cell assumption. It is shown that C-testability of a 1D reversible QCA gate array can be guaranteed for single fault. Theory and circuit examples show that error masking can occur when multiple faults are considered.