An optimal design of conservative efficient reversible parity logic circuits using QCA

Abstract

Quantum-dot Cellular Automata (QCA) is a new nano-innovation in digital systems. It is a possible alternative to ordinary CMOS technology. It offers several advantages in reversible logic such as small size and low power dissipation. Therefore, lots of attentions have been paid to implement different reversible QCA circuits. In this way, an improved model of low power odd-parity-bit, generator and checker have been proposed based on the reversible Feynman gate. The proposed reversible odd-parity-bit, generator and checker can be used to check/detect bit loss of information in telecommunication network systems. The proposed parity generator is 57% faster and occupies 38% lesser area than the previous best design. Furthermore, the proposed Nano-communication system dissipates 65% less energy at 0.5 Ek tunneling energy level. A detailed performance evaluation and power analysis are performed in different aspects to authenticate our proposed bit preservation circuits have superb performance in comparison to previously reported works. The results of the proposed circuits have been verified using QCA Designer and the power calculations have been carried out using QCA Pro tool.