Reversible Gates Research Articles

Reversible Logic based Cryptography Design Algorithm using Random Keys

Reversible computations, besides quantum computing, have various applications in digital signal processing, nanotechnology and bioinformatics. They are particularly useful in designing low-power devices and improving computational efficiency. Cryptography is vital for protecting sensitive information in fields such as bioinformatics and digital signal processing where private data is frequently exchanged. However, cryptographic algorithms can consume significant power and require large areas, particularly when implemented in hardware. Reversible logic gates offer a potential solution by being more power-efficient and potentially reducing implementation area. Using random numbers as keys for both encryption and decryption in a reversible logic gate-based cryptographic algorithm can enhance security. LSB watermarking is a technique to embed additional metadata into digital media, improving data security. To evaluate the performance of the Field Programmable Gate Array for the Reversible Logic Gate Cryptography Design architecture, comparing it to the other state-of-the-art approach is necessary.

Fault-tolerant reversible logic gate-based RO-PUF design

Physically Unclonable Function (PUF) is an emerging modern approach to the security concerns of the physical systems which require the protection of sensitive data. PUF generates unique, reliable, and secure responses which can be utilized for cryptographic applications. In this paper, a fault-tolerant reversible logic gate-based RO PUF is proposed. We utilized a fault-tolerant reversible logic Double Feynman Gate in place of conventional inverters to design the ring oscillators (RO). The proposed RO PUF designs implemented and evaluated on the Basys-3 Artix-7 FPGA board. The PUF parameters such as uniqueness, reliability, and uniformity were analyzed based on the experimental results. The empirical results show that the proposed RO PUF has uniqueness and reliability of 0.49 and 85.95%, respectively. The inter-chip and intra-chip uniqueness for the proposed design is 23% and 25.5%, respectively higher than the conventional RO PUF design. This fault-tolerant reversible logic gate-based RO PUF design shows better uniqueness, reliability, and uniformity than other considered PUF designs.

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Reversible logic can provide lower switching energy costs relative to all irreversible logic, including those developed by industry in semiconductor circuits, however, more research is needed to understand what is possible. Superconducting logic, an exemplary platform for both irreversible and reversible logic, uses flux quanta to represent bits, and the reversible implementation may switch state with low energy dissipation relative to the energy of a flux quantum. Here we simulate reversible shift register gates that are ballistic: their operation is powered by the input bits alone. A storage loop is added relative to previous gates as a key innovation, which bestows an asynchronous property to the gate such that input bits can arrive at different times as long as their order is clearly preserved. The shift register represents bit states by flux polarity, both in the stored bit as well as the ballistic input and output bits. Its operation consists of the elastic swapping of flux between the stored and the moving bit. This is related to a famous irreversible shift register, developed prior to the advent of superconducting flux quanta logic (which used irreversible gates). In the base design of our ballistic shift register (BSR) there is one 1-input and 1-output port, but we find that we can make other asynchronous ballistic gates by extension. The gate constitutes the first asynchronous reversible 2-input gate. Finally, for a better insight into the dynamics, we introduce a collective coordinate model. We find that the gate can be described as motion in two coordinates subject to a potential determined by the input bit and initial stored flux quantum. Aside from the favorable asynchronous feature, the gate is considered practical in the context of energy efficiency, parameter margins, logical depth, and speed.

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

AbstractMost error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

An efficient three-level nano-design for reversible gate using quantum dot-cellular automata with cost analysis

Quantum-dot Cellular Automata (CA) is a suitable nanotechnology for replacing CMOS circuits. The majority, inverter, and reversible structures, are the primary building blocks in quantum-dot CA circuits. Since the reversible gates have recently attained great attention, this paper proposes a new design of a reversible building block based on the Feynman gate. The proposed quantum-dot CA-based Feynman gate is denser and has low delay than the existing circuits. This paper also tests the possible implementation of the proposed design in quantum-dot CA. The QCADesigner is employed to test the functionality of the proposed structure. The proposed efficient quantum-dot CA-based Feynman gate has only 36 cells in three-layer. It consumes 0.03 µm2, which is the smallest among all previous designs. A quantum-cost comparison of the proposed reversible Feynman gate with conventional reversible gates demonstrates the cost-effectiveness of quantum-dot CA. The simulation result matched the truth table of the Feynman gate, indicating that the suggested quantum-dot CA architecture is functional. The proposed architecture can also be used for n-bit code converters as well.

Design of Fault Tolerant Array Multiplier Using Parity Preserving Reversible Gate

The digital designs with Reversible logic are more popular now days because of the increased demand of low power usage. Some of the Reversible logic gates are discussed in this paper. This paper also introduces a Parity Preserving Reversible Gate (PPRG) which is used in the fault tolerant devices design such as adders, subtractors and multipliers. The design of an array multiplier by using fault tolerant parallel adders is discussed in this paper. The fault tolerant parallel adders are designed using fault tolerant full adders and half adders and these adders are designed through Parity Preserving Reversible Gate. These adders and multipliers are useful in designing complex circuits such as ALU.

The use of reversible logic gates in the design of residue number systems

Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2<sup>k</sup>, 2<sup>p</sup>-1}. Modulo 2<sup>n</sup>-1, 2<sup>n</sup>, and 2<sup>n</sup>+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2<sup>n</sup>-1, 2<sup>n+k</sup>, 2<sup>n</sup>+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.

A New Design of a 3 × 3 Reversible Circuit Based on a Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is the best-suggested nanotechnology for designing digital electronic circuits. It has a higher switching frequency, low-power expenditures, low area, high speed and higher scale integration. Recently, many types of research have been on the design of reversible logic gates. Nevertheless, a high demand exists for designing high-speed, high-performance and low-area QCA circuits. Reversible circuits have notably improved with developments in complementary metal–oxide–semiconductor (CMOS) and QCA technologies. In QCA systems, it is important to communicate with other circuits and reversible gates reliably. So, we have used efficient approaches for designing a [Formula: see text] reversible circuit based on XOR gates. Also, the suggested circuits can be widely used in reversible and high-performance systems. The suggested architecture for the [Formula: see text] reversible circuit in QCA is composed of 28 cells, occupying only 0.04[Formula: see text][Formula: see text]m2. Compared to the state-of-the-art, shorter time, smaller areas, more operational frequency and better performance are the essential benefits of the suggested reversible gate design. Full simulations have been conducted with the utilization of QCADesigner software. Additionally, the proposed [Formula: see text] gate has been schematized using two XOR gates.

Simulation of reversible molecular mechanical logic gates and circuits.

Landauer's principle places a fundamental lower limit on the work required to perform a logically irreversible operation. Logically reversible gates provide a way to avoid these work costs and also simplify the task of making the computation as a whole thermodynamically reversible. The inherent reversibility of mechanical logic gates would make them good candidates for the design of practical logically reversible computing systems if not for the relatively large size and mass of such systems. In this paper we outline the design and simulation of reversible molecular mechanical logic gates that come close to the limits of thermodynamic reversibility even under the effects of thermal noise, and outline associated circuit components from which arbitrary combinatorial reversible circuits can be constructed and simulated. We demonstrate that isolated components can be operated in a thermodynamically reversible manner, and explore the complexities of combining components to implement more complex computations. Finally, we demonstrate a method to construct arbitrarily large reversible combinatorial circuits using multiple external controls and signal boosters with a working half-adder circuit.

A new design for XOR gate-based reversible double Feynman gate in nano-scale quantum-dots

Quantum-dot Cellular Automata (QCA), which provides a novel technique for fabricating energy-efficient nano-scale digital circuits, can replace transistor-based technologies. But, in this technology, designing a reliable and reversible circuit design is very important. The use of reversible logic gates in QCA has piqued the interest of a wide range of researchers. However, designing QCA-based architecture for reversible logic circuits still has ample space. The previous circuits in this field have some disadvantages, such as the lack of easy access to inputs and outputs, low speed, and a high number of consumed cells, which have caused the lack of expandability of circuits. Therefore, there is a need to design smaller and faster circuits with easier access to inputs and outputs so that in addition to achieving high speed, reversibility can be extended to other circuits as well. As a result, this study presents a helpful topology for implementing a reversible circuit based on the innovative XOR gate. In this design, a reversible circuit is designed using 2 two-input XOR gates, cell arrangement, and columbic repulsion. It can be integrated with other gates to test the performance of the circuit, its reversibility, and its expansion. To test the extendability of the proposed circuit, we also considered a 4-bit binary to gray code converter. The suggested ideas are tested by running simulations using the QCADesigner-E. The suggested construction consists of 19 cells and takes up only 0.03 µm2. The results confirmed that the design has stable and applicable size, cost, and structures. The proposed architecture is also simple to use on bigger circuits and offers easy access to input and output.

Design of Optically Controlled Reversible NOT Gate Using Micro Ring Resonators

Micro Ring Resonator (MRR) is a successful micro-device with the help of which different types of optical logic gates, logic processors, arithmetic units, etc. can be designed and integrated easily into the modern high-speed communication network. In this article, at first, the author has explained the switching mechanism of MRR and then designed an optically controlled Feynman gate (i.e. reversible controlled-Not gate) using MRRs. The switching mechanism of MRR is reliable and the switching speed of MRR is very fast. The change the resonance condition of MRR can occur when the ring is exposed in the optical pump beam with high intensity. The logic processors using Reversible Logic gates are more acceptable due to their data recovery capability and low power consumption. The designed circuit of optically controlled NOT Gate is testified with the MATLAB simulation results. To fulfil the demand for an ultra-high-speed network, the development of high speed optical logic processors is the primary requisite and this scheme will be very helpful for developing such elements.

Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis

<p><span>The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements.</span></p>

Novel Quantum-Dot Cellular Automata-Based Gate Designs for Efficient Reversible Computing

Reversible logic enables ultra-low power circuit design and quantum computation. Quantum-dot Cellular Automata (QCA) is the most promising technology considered to implement reversible circuits, mainly due to the correspondence between features of reversible and QCA circuits. This work aims to push forward the state-of-the-art of the QCA-based reversible circuits implementation by proposing a novel QCA design of a reversible full adder\full subtractor (FA\FS). At first, we consider an efficient XOR-gate, and based on this, new QCA circuit layouts of Feynman, Toffoli, Peres, PQR, TR, RUG, URG, RQCA, and RQG are proposed. The efficient XOR gate significantly reduces the required clock phases and circuit area. As a result, all the proposed reversible circuits are efficient regarding cell count, delay, and circuit area. Finally, based on the presented reversible gates, a novel QCA design of a reversible full adder\full subtractor (FA\FS) is proposed. Compared to the state-of-the-art circuits, the proposed QCA design of FA\FS reversible circuit achieved up to 57% area savings, with 46% and 29% reduction in cell number and delay, respectively.

Design of a reversible ALU using a novel coplanar reversible full adder and MF gate in QCA nanotechnology

Design of a reversible ALU using a novel coplanar reversible full adder and MF gate in QCA nanotechnology

A Space-Efficient Universal and Multi-Operative Reversible Gate Design Based on Quantum-Dots

Because of the high speed, low-power consumption, low latency and possible use at the atomic and molecular levels, Quantum-dot Cellular Automata (QCA) technology is one of the future nanoscale technologies that can replace the present transistor-based technology. For the purpose of creating QCA circuits, reversible logic can be regarded as an appropriate candidate. In this research, a new structure for multi-operative reversible designs is suggested. The Saeid Nima Gate (SNG), proposed in this research study, is a brand-new, incredibly effective, multi-operative, universal reversible gate implemented in QCA nanotechnology employing both majority and inverter gates. Reversible gates, also known as reversible logic gates, are gates that have n inputs and n outputs, which is an equal number of inputs and outputs. The amount of energy lost during computations will be reduced if the numbers of inputs and outputs are identical. The proposed gate is modified and reorganized to optimize further, employing exact QCA cell interaction. All fundamental logic gates are implemented using it to demonstrate the universality of the proposed SNG. Reversible logic has advanced, and as a result, our suggested solution has a lower quantum cost than previously reported systems. The suggested design is simulated using the QCADesigner-E tools.

Design and analysis of 3 × 3 reversible quantum gates

Design and analysis of 3 × 3 reversible quantum gates

A New Nano-Scale and Energy-Optimized Reversible Digital Circuit Based on Quantum Technology

A nano-scale quantum-dot cellular automaton (QCA) is one of the most promising replacements for CMOS technology. Despite the potential advantages of this technology, QCA circuits are frequently plagued by numerous forms of manufacturing faults (such as a missing cell, extra cell, displacement cell, and rotated cell), making them prone to failure. As a result, in QCA technology, the design of reversible circuits has received much attention. Reversible circuits are resistant to many kinds of faults due to their inherent properties and have the possibility of data reversibility, which is important. Therefore, this research proposes a new reversible gate, followed by a new 3 × 3 reversible gate. The proposed structure does not need rotated cells and only uses one layer, increasing the design’s manufacturability. QCADesigner-E and the Euler method on coherence vector (w/energy) are employed to simulate the proposed structure. The 3 × 3 reversible circuit consists of 21 cells that take up just 0.046 µm2. Compared to the existing QCA-based single-layer reversible circuit, the proposed reversible circuit minimizes cell count, area, and delay. Furthermore, the energy consumption is studied, confirming the optimal energy consumption pattern in the proposed circuit. The proposed reversible 3 × 3 circuit dissipates average energy of 1.36 (eV) and overall energy of 1.49 (eV). Finally, the quantum cost for implementing the reversible circuits indicates a lower value than that of all the other examined circuits.

Electrolyte-gate-driven carrier density modulation and metal–insulator transition in semiconducting epitaxial CdO films

CdO has drawn much recent interest as a high-room-temperature-mobility oxide semiconductor with exciting potential for mid-infrared photonics and plasmonics. Wide-range modulation of carrier density in CdO is of interest both for fundamental reasons (to explore transport mechanisms in single samples) and for applications (in tunable photonic devices). Here, we thus apply ion-gel-based electrolyte gating to ultrathin epitaxial CdO(001) films, using transport, x-ray diffraction, and atomic force microscopy to deduce a reversible electrostatic gate response from −4 to +2 V, followed by rapid film degradation at higher gate voltage. Further advancing the mechanistic understanding of electrolyte gating, these observations are explained in terms of low oxygen vacancy diffusivity and high acid etchability in CdO. Most importantly, the 6-V-wide reversible electrostatic gating window is shown to enable ten-fold modulation of the Hall electron density, a striking voltage-induced metal–insulator transition, and 15-fold variation of the electron mobility. Such modulations, which are limited only by unintentional doping levels in ultrathin films, are of exceptional interest for voltage-tunable devices.

Novel high-performance QCA Fredkin gate and designing scalable QCA binary to gray and vice versa

In the design of digital logic circuits, QCA technology is an excellent alternative to CMOS technology. Its advantages over CMOS include low power consumption, fast circuit switching, and nanoscale design. Circuits that convert data between different formats are code converters. Code converters have an essential role in high-performance computing and signal processing. In this paper, first, we proposed a novel QCA structure for the quantum reversible Fredkin gate. Second, we proposed 4-bit and 8-bit QCA binary-to-gray converter and vice versa. For the second proposal, both reversible and irreversible structures are suggested. The proposed structures are scalable up to N bits. To change the conversion type from B2G to G2B, we use a 2:1 QCA multiplexer. The proposed QCA Fredkin is applied in the reversible design of QCA code converters as multiplexers. The suggested designs are simulated using the QCADesigner tool. Then we calculated figures of merit, including cell counts, occupied areas, and clock zones. Finally, we compare the proposed structures to existing research. Our proposed approach is the first quantum-dot cellular automata design to perform B2G conversion and G2B in a single QCA circuit. The proposed designs are scalable. Specifications are reported.

A Logically Reversible Double Feynman Gate with Molecular Engineered Bacteria Arranged in an Artificial Neural Network-Type Architecture.

Reversible logic gates are the key components of reversible computing that map inputs and outputs in a certain one-to-one pattern so that the output signals can reveal the pattern of the input signals. One of the main research foci of reversible computing is the implementation of basic reversible gates by various modalities. Though true thermodynamic reversibility cannot be attained within living cells, the high energy efficiency of biological reactions inspires the implementation of reversible computation in living cells. The implementation of synthetic genetic circuits is mostly based on conventional irreversible computing, and the implementation of logical reversibility in living cells is rare. Here, we constructed a 3-input-3-output synthetic genetic reversible double Feynman logic gate with a population of genetically engineered E. coli cells. Instead of following hierarchical electronic design principles, we adapted the concept of artificial neural networks (ANN) and built a single-layer artificial network-type architecture with five different engineered bacteria, named bactoneurons. We used three extracellular chemicals as input signals and the expression of three fluorescence proteins as the output signals. The cellular devices, which combine the input chemical signals linearly and pass them through a nonlinear activation function and represent specific bactoneurons, were built by designing and creating small synthetic genetic networks inside E. coli. The weights of each of the inputs and biases of individual bactoneurons in the bacterial ANN were adjusted by optimizing the synthetic genetic networks. When arranging the five bactoneurons through an ANN-type architecture, the system generated a double Feynman gate function at the population level. To our knowledge, this is the first reversible double Feynman gate realization with living cells. This work may have significance in development of biocomputer technology, reversible computation, ANN wetware, and synthetic biology.