Reverse Converter Research Articles

A Generalized Residue Number System Design Approach for Ultralow-Power Arithmetic Circuits Based on Deterministic Bit-Streams

The peak power consumption has become an important concern in the hardware design process of some of today’s applications, such as Energy Harvesting (EH) and Bio-Implantable (BI) electronic devices. The limited peak harvested power in EH devices and heating concerns in BI devices are the main reasons for power control’s importance in these devices. This paper proposes a generalized design approach for ultra-low-power arithmetic circuits. The proposed circuits are based on Residue Number System (RNS) combined with deterministic bit-streams. The resulting circuits can be used in systems with a restricted power budget. We suggest several approaches to design generic hardware-efficient adders, multipliers, multiply-accumulate units (MAC), forward converters (FC), and reverse converters (RC). Using the proposed approach, designing these components for any moduli of the RNS can be performed through simple bit-width adjustments in the circuits. The synthesis results show that the proposed adder achieves, on average, 69% and 2% lower area compared to the bit-serial and a state-of-the-art RNS adder, respectively. Furthermore, the proposed multiplier outperforms the bit-serial, interleaved, and a state-of-the-art design for multiplying RNS numbers by, on average, 57%, 60%, and 77% in terms of power consumption, respectively. The efficiency of our approach is shown via two essential applications, digital signal processing and machine learning. We implement an FFT engine using the proposed method. Compared to prior RNS implementations, our design achieves 47% lower power consumption. We also implement a CNN accelerator’s Processing Element (PE) with the proposed computation elements. Our design provides considerable speedup and lower power consumption compared to a state-of-the-art ultra-lower-power design.

Design of reverse converters for the general RNS 3-moduli set {2k, 2n − 1, 2n + 1}

This paper presents a new design method of the reverse (residue-to-binary) converter for the flexible 3-moduli residue number system (RNS) set { 2^k, 2^n-1, 2^n+1 }, where k and n are a pair of arbitrary integers ge 2. The basic equation of the reverse converter is formulated in two alternative forms, each of which consists of two separate parts: one depending on input variables of the converter, and the other being a single constant. The constant can be either added inside the reverse converter or shifted out to the residue datapath channels, in most cases at no hardware cost or extra delay. From the set of basic functions, which are essentially different than those of the only two known general converters proposed for this moduli set, four versions of a converter can be designed for any pair of k and n. Experimental results obtained using the commercial 65-nm low-power design kit and industrial synthesis tools for all dynamic ranges from 8 to 40 bits suggest that, compared to the state-of-the-art designs, at least one version of the newly proposed converters is superior w.r.t. delay, power consumption, and area, for all dynamic ranges considered. The savings for the best versions (these with constants moved to the datapath channels) are up to 12.7% for the area and from 2.5% to 14% (5.8 % on average) for the delay, while the power consumption is reduced up to 23.2% (5.6% on average).

Measuring 3- and 4-Moduli Sets Delay Per Bit in Residue Number System: A Survey

Given the efficiency of the residue number system in high-speed and low-power applications, a wide variety of moduli sets have been introduced in the literature. Selecting an appropriate moduli set is one of the most important issues of using a residue number system. Moduli sets can be evaluated by several factors such as dynamic range, balanced channels, fast and low-power modular operations, and efficient reverse converter. In this paper, 3- and 4-moduli sets are separately reviewed and compared from a different perspective. Furthermore, the most efficient 3- and 4-moduli sets are suggested. A new parameter for average delay comparison is introduced, which shows the delay of every bit in the dynamic range providing a fair comparison of moduli sets with different numbers of moduli. Our comparison showed that either balanced channels or the delay of computations are essential factors for designing an efficient new moduli set.

The use of reversible logic gates in the design of residue number systems

Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2<sup>k</sup>, 2<sup>p</sup>-1}. Modulo 2<sup>n</sup>-1, 2<sup>n</sup>, and 2<sup>n</sup>+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2<sup>n</sup>-1, 2<sup>n+k</sup>, 2<sup>n</sup>+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.

Optimized reverse converters with multibit soft error correction support at 7nm technology

Residue number system (RNS) speeds up digital signal processing systems involving dominant addition and multiplication. Addition and multiplication are accelerated further and performed with a balanced performance on one-hot coded (OHC) residue digits. However, the high complexity of the RNS reverse converter (RC) may kill the performance gain. This paper proposes a high-speed and scalable RNS-RC for both regular and one-hot RNS. For redundant RNS (RRNS), an RRNS-RC is proposed, which based on majority-voting between OHC residue digits, corrects multibit soft errors occurring in a single residue channel. With pass-transistor logic and low-power FinFETs, the proposed RCs are optimized. The simulated RRNS-RC corrected 98.5% of soft errors, while consuming 7, 6.2 and 0.4% of the system's area, leakage power and dynamic power, respectively. As compared to the leading lookup table RC in the literature, RNS-RC exhibited 10.3X, 4.4X and 1.8X savings in area, average power, and delay, respectively.

Residue Number System-Based Approach to Minimise Energy Consumption in Wireless Sensor Networks

This study harnesses the useful number properties of the residue number system (RNS) to minimise energy consumption in a wireless sensor network. In a traditional cluster-based wireless sensor network, large bit representations of aggregated packets are transmitted to the base station. However, large bit patterns of packets are slower compared to smaller bits. The proposed approach splits aggregated data into a pre-specified number of transmission channels using a moduli set. Cheap energy cost routes from the cluster heads are computed to deliver the chunked aggregated data to the base station. Forward and reverse converters are proposed to encode data into RNS and decode the RNS data that reaches the base station. MATLAB simulation is used to implement the proposed data splitting method and to evaluate network performance. The experimental results suggest that the proposed method is more effective at minimising transmission energy when compared with traditional approaches in which complete packets are transmitted.

Ultra-Low-Power Modulo Adder with Thermometer Coding for Uncertain RNS Applications

The residue numeral system (RNS) is a numerical representation of integers based on modulo values. The RNS makes computing systems more efficient in terms of speed, power, energy, area, and other considerations. In recent years, the RNS has focused on a variety of topics, including digital signal and image processing, cryptography, embedded systems (ESs), communications, and the Internet of Things (IoT), among others. Forward and reverse converters, as well as arithmetic units in the channels, all use modular addition. In low-power ESs, thermometer coding (TC) has lately been utilized to reduce uncertainty. The thermometer code (TC) is more energy-efficient and consumes less power for modulo addition as compared to binary adders. Based on TC, the proposed research develops a power-efficient modular adder. The proposed design is simulated using Cadence’s NC launch encounter tool. In comparison with conventional modular adders, the proposed modular adder consumes 40% and 35% less power for one-hot coding modulo adder and thermometer code residue (TCR) modulo adder, respectively.

Design of an Efficient Reverse Converter for Moduli Sets

The appropriate selection of moduli has a significant impact on the reverse converter's speed and complexity. The modified converter depends upon the arithmetic designs that are implemented without the read - only memories and lookup tables. The Carry Save Adder and Carry Propagate Adder are used in the reverse converter and modulo adder gives higher speed and less hardware complexity. The proposed converter has been implemented to get the conversion time and area as supported by the reverse converter of 12-bits and maximum up to 100-bits.

Secured Paillier Homomorphic Encryption Scheme Based on the Residue Number System

In this paper, we present an improved Paillier Cryptosystem for a secured data transmission based on the Residue Number System (RNS). The current state of Paillier Cryptosystem allows the computation of the plaintext from the cipher text without solving its security assumption of Decisional Composite Residuosity or the knowledge of its private keys under mathematical attacks. The proposed RNS based cryptosystem involving two stages of encryption and two stages of decryption has never been adequately studied before. This paper attempts to solve by introducing two stages of encryption and two stages of decryption. The first stage of the encryption process maintains the traditional Paillier encryption process and the second stage process is the encryption using the recommended moduli set – by the RNS Forward converter. At the first stage of the decryption process, our proposed RNS based reverse converter is adopted and finally, the traditional Paillier decryption process will be used at the second stage of the decryption process. Because the entire encryption technique is randomized, it can withstand chosen bruteforce attacks. The suggested algorithm's security study reveals that it has a wide key space ( , a high level resistance to key sensitivity attacks, and an acceptable level of resilience. In terms of security, it has been discovered that the proposed system outperforms the present algorithm.

Magnitude Comparison and Sign Detection based on the 4-Moduli Set {2n+1, 2n−1, 2n+3, 2n−3}

The 4-moduli set residue number system (RNS),{2n+1, 2n−1, 2n+3, 2n−3}, with a wide dynamic range, has recently been proposed as a balanced 4-moduli set for utilizing the cases that demand fast calculations such as deep learning and implementation of asymmetric cryptographic algorithms. Up to now, only an unsigned reverse converter has been designed for this moduli set. Thus, there is a need for two separate units, a sign detection circuit, and a comparator to use this set in cases requiring sign and comparison. Nevertheless, the existence of these components demands high hardware that makes the implementation of the RNS impractical. Therefore, this paper presents the design of a sign detection circuit and a signed reverse converter that can overcome this problem by reusing the hardware. To achieve an integrated hardware design, first, we optimized the previous unsigned reverse converter for this 4-moduli set and next, we derived an approach from the structure of the reverse convertor for detecting signs and recognizing comparators. Finally, using the sign signals extracted from the reverse converter, we change reverse convertor into a unit that perform sign detection and comparison. The simulation has been conducted using ISE Design Suite 14.7 tool and the Spartan6 family technology. Empirical results show that, the proposed multifunctional unit has an approximately identical performance with respect to delay and area compared to the previous reverse converter. Besides, the proposed signed reverse converter relies on a 46% and 28% reduction in area and delay compared to the previous unsigned reverse converter which uses a comparator and also a multiplexer to detect a sign in the output.

Effective Error Control Scheme in Real-Time Wireless Sensor Networks

Wireless Sensor Networks (WSNs) subsist on network of huge numbers of hubs that are distributed in unfriendly environments used for habitat monitoring and to observe changes in phenomena. These hubs are susceptible to faults such as energy exhaustion, hardware glitches, communication link errors, malicious attacks, which may lead to errors in message delivery. However, these systems are typically utilized to convey vital information in remote places. Thus, efficient error identification and correction is thereby required in order to maintain the accuracy of the received message. This paper aimed at designing high speed reverse converter for effective error control codes using Redundant Residue Number System in order to enhance the accuracy of messages delivered for real-time WSNs. In order to attain a greater error correction, a reverse converter which was based on Mixed Radix Conversion was designed for the moduli set {2n+1-1, 2n, 2n-1}. In addition to this moduli, an extra redundant moduli set{2n+1+3, 22n - 3} is also designed for higher correctness. For correction and identification of corrupted values in the original data, maximum likelihood was used. The results obtained show that the suggested moduli set offers low energy utilization and consistency of the received message in real time WSNs.

Design of Efficient Reverse Converters for Residue Number System

The main factors that affect the performance of residue number system (RNS) are speed and hardware complexity of the residue-to-binary converter. In this paper, two efficient reverse converters are proposed for the moduli sets [Formula: see text] and [Formula: see text] based on two-level approach. In the first level, a reverse converter is implemented based on new Chinese remainder theorem-I for the moduli set [Formula: see text]. The fourth modulus is joined in the second level for each converter and only simple binary adders are used in this level. The architecture of novel circuits mainly consists of simple adders thus leading to implementing efficient converters. To have a fair comparison, both unit gate model and simulation are used. The proposed converters and the recently represented converters have been implemented on Xilinx ISE 13.1 field-programmable gate array (FPGA) simulator to derive area and delay that are measured for the various ranges up to 256 bits. The experimental results show that the proposed converters have lower area–time complexity comparing to the state-of-the-art converter for similar moduli sets.

Efficient Incorporation of the RNS Datapath in Reverse Converter

The class of moduli sets in the form of {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> , 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> +1, m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> } with m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ∈ {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sup> +1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sup> -1} has earned significant popularity in the implementation of the Residue Number System (RNS)-based computational systems, mainly thanks to the efficient arithmetic unit and a high degree of parallelism. However, its complicated inter-modulo computation leads to a high overhead associated with the complex reverse converter. This overhead is the main barrier for energy-efficient implementation of RNS-based devices, particularly for edge computing applications. This brief presents a new approach that embeds the reverse converter into the arithmetic unit of the RNS processor for the aforesaid well-known class of moduli sets. The effective hardware reuse in the proposed approach leads to an area and energy-efficient RNS realization for this class of moduli set. The experimental results based on 65 nm CMOS technology indicate the superiority of RNS realization by employing the proposed design methodology. The proposed architecture for a given RNS provides a substantial 17.4% area-saving and 13.32% less power-consumption on average compared to the traditional design approach, with the negligible penalty in delay.

A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set

The high dynamic range residue number system (RNS) five-moduli { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } has been recently introduced as an arithmetically balanced five-moduli set for computation-intensive applications on wide operands such as asymmetric cryptography algorithms. The previous dedicated design of RNS components for this moduli set is just an unsigned reverse converter. In order to utilize of the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } in applications handling with signed numbers, two important components are needed: Sign Detector and Signed Reverse Converter. However, having both of these components results in high hardware requirements which makes RNS impractical. This paper overcomes to this problem by designing a unified unit which can perform both signed reverse conversion as well as sign detection through the reuse of hardware. To the authors knowledge, this is the first attempt to design sign detector for a moduli set including 2n±3 moduli. In order to achieve a hardware-amenable design, we first improved the performance of the previous unsigned reverse converter for the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 }. Then, we extract a sign detection method from the structure of the reverse converter. Finally, we make the unsigned reverse converter to sign converter through the use of the extracted sign signal from the reverse converter. The experimental results shown that the proposed multifunctional unit has relatively the same performance in terms of area, delay and power-consumption than the previous unsigned reverse converter for the set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } while it can perform two complex signed operations.

Efficient two-level reverse converters for the four-moduli set {2n−1, 2n–1, 2n−1–1, 2n+1–1}

In this paper, 2 efficient reverse converters are introduced for the four-moduli set {2n−1, 2n–1, 2n−1–1, 2n+1–1} which offers a high speed arithmetic unit due to its balanced modulus in the form of 2 k and 2 k–1. The proposed converters are designed in two-level architecture. ROM free and adder base structures are the advantages of the proposed converters which result in efficient implementation in VLSI circuits. New Chinese remainder theorem 1 (New CRT-I) and mixed radix conversion (MRC) algorithms are used to design the first and second proposed reverse converters, respectively. For the various dynamic ranges (DR), theoretical results based on unit gate model show that the proposed reverse converters have a better Area-Time (AT) metric in comparison to the reverse converters of the other similar four moduli set in the literature. Also based on FPGA implementation results,the proposed convertersoffer lower AT metric on average 12% and 10% when comparing with the latest design for similar the moduli set {2n, 2n+1–1, 2n–1, 2n−1–1}.

Designing reverse converter for data transmission systems from two-level RNS to BNS

In this paper, we present a reverse conversion from a two-stage Residue Number System (RNS) to a Binary Number System (BNS) with a special set of level 1 modules {2 α1, 2 α2 − 1, …, 2αn − 1} and level 2 modules {2 β1, 2 β2 − 1, …, 2 β k − 1}. The proposed method is based on the Chinese Remainder Theorem (CRT) with fractions and using a calculation method that uses constant multiplications to speed up calculations. This article discusses the simulation of FPGA reverse conversion to a two-stage RNS using the proposed method and the standard CRT using adders, their comparison of latency and hardware costs.

An improved RNS-to-binary converter for 7-modulus set {2n–5–1, 2n–3–1, 2n–2+1, 2n–1–1, 2n–1+1, 2n, 2n+1} for n even

In this paper a residue-to-binary converter for the 7-modulus set {2n–5–1, 2n–3–1, 2n–2+1, 2n–1–1, 2n–1+1, 2n, 2n+1} for n even is presented, which is an improved version of a reverse converter presented recently. The proposed converter needs less hardware resources ranging from 52.9% to 66.9%, conversion time of 68–70.7% and power dissipation of 47–63% of those needed for an earlier described converter for the same considered dynamic ranges.

On reverse converters for arbitrary multi-moduli RNS

In this paper, we propose a new design of reverse converters for residue number systems with arbitrary moduli sets consisting of any number of odd moduli and one even modulus of the type 2k. The new converters are arithmetic-based designs, that may be implemented using only arithmetic components without any read-only memories nor lookup tables. We tackle the problem of large modular reduction imposed by the properties of Chinese Remainder Theorem (CRT) employed in our method by calculating small correction factor in parallel with weighted sum of CRT in a set of constant multipliers followed by one two-operand modulo adder. Synthesis results show delay reduction over existing designs of up to 39.23% with area reductions of up to 28.48%.

Сравнительный анализ тиристорных схем управления двигателями постоянного тока, применяемых на судах

The article considers the problem of the DC motors control that are often used in many electric drive systems. Due to the progress of industrial electronics and technology it has become possible to develop more efficient motor control circuits. The conventional speed control methods commit power losses in the system, which can be minimized by using the power electronics strategy. There is considered the thyristor control of DC motors of the ship electric drive. The DC motor control systems are described and simulation models in the MATLAB Simulink program are presented. The thyristor methods for controlling a DC motor speed are listed: single-phase semi-controlled converter (for motors with power up to 15 kW); single-phase drive with a controlled converter (available to operate in two quadrants); three-phase semi-controlled converter; three-phase controlled converter; single-phase reverse converter realized by connecting two single-phase converters (ensuring multi-mode operation); three-phase reverse converter realized as a single-phase converter. The mechanical characteristic of a DC motor was illustrated when the voltage supplied to the armature winding changed. It has been stated that control of the armature voltage is more favorable for speeds below the rated speed; flow control is preferable for speeds above the nominal speed. It has been inferred that speed control by means of power electronics devices provides large energy savings, in contrast to the traditional speed control methods, since the traditional methods experience significant energy losses.

Towards the Integration of Reverse Converters into the RNS Channels

The conversion from a Residue Number System (RNS) to a weighted representation is a costly inter-modulo operation that introduces delay and area overhead to RNS processors, while also increasing power consumption. This paper proposes a new approach to decompose the reverse conversion into operations that can be processed by the arithmetic units already present in the RNS independent channels. This leads to a more effective reuse of the processor circuitry while enhancing parallelism. Experimental results show that, when the proposed techniques are applied to architectures based on ripple-carry adders for the traditional 3-moduli set, the delay is improved in average by 16 percent, the circuit area by 36 percent and the power consumption by 47 percent. When carry-lookahead adder topologies are considered, these improvements are in average of 45 percent for the circuit area and 58 percent for the power consumption while the delay is only slightly reduced. The proposed techniques are applied to a use case in digital filtering, showing an increase in throughput/area of up to 1.25 times, and average reductions in energy consumption of 15.6 percent. This work is a step forward to the usage of RNS in practice, since reverse conversion underpins other hard inter-modulo operations, like comparison, scaling and division.