Resynchronization Mechanism Research Articles

Highly Accurate Clock Synchronization With Drift Correction for the Controller Area Network

Modern vehicles, that have to be considered as safety-critical cyber-physical systems, require highly accurate <i>clock synchronization</i> (CS) among their distributed computing devices. Since Controller Area Network (CAN) is the predominant in-vehicle communication bus, it is highly relevant to support CS for CAN. This article proposes an original CS method for distributed in-vehicle networks based on CAN with both <i>offset</i> and <i>drift correction</i> . While offset correction is performed based on timestamps in periodic reference messages (RMs), our new method benefits from the re-synchronization mechanism of the CAN bit timing to apply highly accurate drift correction. Our algorithm does not make any modifications to the CAN protocol but requires the measurement of the phase error from the CAN controller. We derive analytical bounds for the expected clock differences and further validate the practicability of the proposed method by comprehensive experiments. As the main result, our method achieves a clock accuracy below <inline-formula><tex-math notation="LaTeX">$2\;\mu$</tex-math></inline-formula> s independent of important parameters such as the bit rate, RM period, bus utilization and time-varying clock drifts.

Readout Firmware of the Vertex Locator for LHCb Run 3 and Beyond

The new LHCb Vertex Locator (VELO) for LHCb, comprising a new pixel detector and readout electronics, will be installed in 2021 for data taking in Run 3 at the LHC. The electronics centers around the “VeloPix” ASIC at the front-end operating in a trigger-less readout at 40MHz. A custom serializer, called gigabit wireline transmitter (GWT), and associated custom protocol have been designed for the VeloPix. The GWT data are sent from the serializers of the VeloPix at a line rate of 5.12 Gb/s, reaching a total data rate of 2–3 Tb/s for the full VELO detector. Data are sent over 300-m optic-fiber links to the control and readout electronics cards for deserialization and processing in Intel Arria 10 FPGAs. Because of the VeloPix trigger-less design, latency variances up to 12 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> can occur between adjacent datagrams. It is therefore essential to buffer and synchronize the data in firmware prior to onward propagation or suffer a huge CPU-processing penalty. This article will describe the architecture of the readout firmware in detail with focus given to the resynchronization mechanism and techniques for cauterization. Issues found during readout commissioning, and scaling resource utilization, along with the their solutions, will be illustrated. The latest results of the firmware data-processing chain can be presented as well as the verification procedures employed in simulation. Challenges for the next generation of the detector will also be presented with ideas for a readout processing solution.

Error Propagation Mitigation in Sliding Window Decoding of Braided Convolutional Codes

We investigate error propagation in sliding window decoding of braided convolutional codes (BCCs). Previous studies of BCCs have focused on iterative decoding thresholds, minimum distance properties, and their bit error rate (BER) performance at small to moderate frame length. Here, we consider a sliding window decoder in the context of large frame length or one that continuously outputs blocks in a streaming fashion. In this case, decoder error propagation, due to the feedback inherent in BCCs, can be a serious problem. To mitigate the effects of error propagation, we propose several schemes: a window extension algorithm where the decoder window size can be extended adaptively, a resynchronization mechanism where we reset the encoder to the initial state, and a retransmission strategy where erroneously decoded blocks are retransmitted. In addition, we introduce a soft BER stopping rule to reduce computational complexity, and the tradeoff between performance and complexity is examined. Simulation results show that, using the proposed window extension algorithm, resynchronization mechanism, and retransmission strategy, the BER performance of BCCs can be improved by up to four orders of magnitude in the signal-to-noise ratio operating range of interest, and the soft BER stopping rule can be employed to reduce computational complexity.

Cipher chaining key re-synchronization in LPWAN IoT network using a deep learning approach

Low Power Wide Area Network (LPWAN) technology enables low power consumption, long range wireless connectivity, and low cost for strengthening the business cases and achieved eminence as the preferred choice for IoT applications as well. Despite these advantages, they have critical limitations such as very restricted payload size and computation power which creates new challenges in their encryption methods including cipher chaining. A resynchronization mechanism is required in the cipher chaining methods, to sync the keys in case of receiving messages out of order due to events such as packet loss (which is very likely in LPWANs). Since current key resynchronization methods consume a part of the transmitting message, they are not applicable in LPWANs considering their very limited payload size. In this paper, a novel mechanism is proposed for key resynchronization using deep learning. The deep learning is used to learn the pattern of messages and recognize whether or not a message is decrypted corruptly. Then, this model is employed as a tool to identify correct key to decrypt messages. The proposed method enables two parties to keep track of their key sequence without having to add any overload to the payload. Various case studies are provided and simulated to exhibit the efficiency of the proposed method. The case studies proved the robustness of the method in different situations such as single and multiple events loss and different lossy networks. Case studies show up to 99.9% accuracy in key resynchronization with the proposed method after message loss.

Resynchronization of Distributed Generation Based on the Universal Droop Controller for Seamless Transfer Between Operation Modes

Distributed generation (DG) inverters can operate in the islanded mode and the grid-connected mode. When these DG inverters operate in the islanded mode, they often form a microgrid. The magnitude and phase of the main grid voltage deviate from the microgrid voltage. If the microgrid is connected to the main grid under such condition, it results in a high transient overcurrent that is harmful to the system. This article presents a new, simple, and effective resynchronization mechanism for the universal droop control (UDC) DG inverters to achieve a seamless transfer from the islanded mode to the grid-connected mode. Simulation and experimental results are provided to verify the effectiveness of the proposed method. The result shows that the high transient overcurrent can be avoided and a seamless connection/reconnection to the main grid can be achieved.

LBS: A Beacon Synchronization Scheme With Higher Schedulability for IEEE 802.15.4 Cluster-Tree-Based IoT Applications

The IEEE 802.15.4 standard is one of the most widely used link layer technology for building Internet of Things (IoT). It specifies several physical layer options and MAC layer for meeting low-power and low-rate requirements of devices deployed in a network of IoT. The standard also specifies a synchronization scheme for devices connected in a star topology, operating in beacon-enabled (BE) mode using periodic beacons. The BE mode facilitates synchronization among devices for data transmission and is suitable for large networks to establish low duty-cycles. Absence of a such a scheme for a cluster-tree network has confined its application only to nonbeacon mode. The challenge here is to schedule beacon frame transmissions of multiple devices in a nonoverlapping manner to avoid beacon collisions. This paper tackles the problem of synchronization by proposing localized beacon synchronization (LBS) scheme, a distributed technique for beacon scheduling in cluster-tree network topologies. LBS uses 2-hop information and association order to compute beacon transmission offsets that better utilize the available time slots, incur fewer transmissions, and is highly scalable. Further, we analytically show that the schedulability of the proposed scheme is higher compared to other related schemes. In addition, we also address the important issue of resynchronization that has been ignored in all of the prior works. The proposed resynchronization mechanisms consider the interdependencies between synchronization and duty-cycling schemes and are shown to significantly lower the synchronization overhead when synchronization among devices is lost.

A resynchronization attack on stream ciphers filtered by Maiorana-McFarland functions

A resynchronization attack is proposed on stream ciphers filtered by Maiorana-McFarland (M-M) functions and equipped with a linear resynchronization mechanism. The proposed attack utilizes the linear weakness of the resynchronization mechanism, the partial linearity of M-M functions, and applies the linear consistency test method to recover the secret key. It is shown that an M-M function should not be implemented by itself but rather in combination with other nonlinear components in stream ciphers using linear mechanisms to prevent the proposed attack. It is also shown that the use of linear resynchronization mechanisms should be avoided despite their high efficiency in stream ciphers filtered by M-M functions.

Performance overview of the quasi-synchronous operation mode in optical burst switching (OBS) networks

Optical burst switching (OBS) is able to operate under both asynchronous and synchronous burst departures. Although the asynchronous approach is generally assumed in OBS owing to its simplicity and low technical requirements, it has been shown that performance improvements, in terms of the overall burst loss probability, can be achieved under synchronous operation. Moreover, when effective contention resolution mechanisms are applied, such improvements are significant. Since perfect synchronization is not a viable solution, we propose a novel operation mode with relaxed technical requirements, the quasi-synchronous (QS) operation. In this paper, the performance of the QS operation mode is evaluated by an exact analytic expression, assuming a Poisson burst arrival process and a single-wavelength scenario. This mathematical analysis is completed with numerical results that validate its accuracy. Furthermore, we tackle the issue of not having well-aligned clock information between network nodes by proposing a novel re-synchronization mechanism for OBS networks. Finally, a performance study of the QS operation under different deflection routing techniques is presented. The results show that our novel QS approach achieves significant performance benefits with respect to the asynchronous operation while avoiding the architectural complexity of the synchronous scheme.

Digital Control for Radiation-Hardened Switching Converters in Space

Single-event hardening solutions for two converter designs with digital control are considered for space radiation environments: 1) a boost converter using static random access memory (SRAM)-based field programmable gate arrays (FPGAs). In this case the hardening approach is based on duplication at both the logic and device levels and on a nondisruptive resynchronization mechanism that ensures the converter operation if single-event functional interrupt occurs. 2) An integrated buck converter that uses redundancy at the register level, as well as modification of the very high speed integrated circuit (VHSIC) hardware description language (VHDL) code. These hardening techniques are validated through experiments and simulations.

Joint Symbol Synchronization and Turbo Decoding for Photon-limited Optical PPM Channels

We extend the results of similar joint symbol synchronization and decoding schemes proposed earlier by other researchers for joint symbol synchronization and decoding of convolutional sequences via Viterbi decoder, to parallel concatenated convolutional codes and turbo-decoders. We also propose a re-synchronization mechanism such that we restart joint symbol synchronization and decoding again when the synchronization error is significant. The simulation results show that its performance is not far off from that of perfect symbol synchronization and decoding in turbo-coded pulse-position modulation (PPM) optical communication systems in photon-limited channels.

A simple data link protocol for high-speed packet networks

Many popular point-to-point data link protocols use the high-level data link control (HDLC) framing mechanism, which delineates protocol data units (PDUs) by means of a special bit pattern or flag. When such a flag occurs in the payload portion of a frame, an escape byte used to pad the transmitted byte stream enables the receiver to differentiate between a true framing flag and an occurrence of the flag pattern in the user information. The need to process each byte in the incoming byte stream to identify the flag pattern makes this frame delineation method increasingly more complex and expensive to implement as the interface speed increases. In addition, the byte stuffing operation performed when the flag pattern appears in the user information stream expands the carried traffic, interfering with quality of service (QoS) management procedures and making the link susceptible to malicious attacks. These factors limit the scalability and QoS management capabilities of the flag-based data link protocols, particularly at high link rates. The increasing popularity of the packet over SONET (POS) protocol stack makes it desirable to find alternative framing protocols. In this paper, we present a simple data link (SDL) protocol. Based on using a Length Indicator field and a header cyclic redundancy check (CRC), rather than a flag, to delineate frames, SDL is inherently scalable to high speeds and provides constant transmission overhead. We discuss the error control, delineation, and resynchronization mechanisms used by SDL, and we describe a link scrambler designed to protect against malicious attacks that attempt to generate very low bit transition density on the line. We also present additional link control functions designed to make SDL suitable for next-generation multiservice networks.