RESURF Devices Research Articles

A Uni-gate vertical power MOSFET with improved figure of Merits: Design and analysis

In this paper, we propose and analyze a single buried gate power MOSFET structure. The structure uses single gate buried under the source and channel region with its dimensions optimized to get the best Ron-BV tradeoff. The device exhibits a good scaling property without performance degradation, which our previous structure of dual buried gates power MOSFET lacks because of the coupling effect of the two gates. The performance of the dual gates device depends largely on the length of the gates as well as on the separation between them. A performance degradation is observed while scaling it, in order to reduce its specific ON resistance. The proposed single gate device eliminates the coupling effect of the two gates allowing a better scaling of the device together with decreased process sensitivity. The scaling reduces the active area of the proposed device, resulting in the lowering of its specific ON resistance, without any significant change in its breakdown voltage. The reduced gate coupling also allows a high drift doping which further reduces the on resistance. The simulation results using TCAD device simulator shows that the proposed device possess a specific ON resistance of 25.31mohm.mm2 at a breakdown voltage of 68 V, resulting in a Baliga’s Figure-of-merit (FOM1) of 17.99 MW/cm2, which is highest among the other reported non RESURF devices in the literature. This is achieved in parallel with the reduced gate charge resulting in a good reduction in its other figure of merit, FOM2 (RspxQsp).

Analytical Design and Experimental Verification of Lateral Superjunction Based on Global Region Normalization Method

The global region normalization (GRN) method is proposed to optimize the lateral superjunction (SJ), in this article. The GRN features normalizations in the global doping range of the SJ from zero to the maximum doping concentration N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> that was theoretically determined by the pillar width W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SJ</sub> . Then the optimization covers all the possible design points of the SJ. For the SJ with given W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SJ</sub> and pillar length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SJ</sub> , the specific ON-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> and breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> are normalized in the global region of the doping concentration N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SJ</sub> . With the GRN method, the global normalization function f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</sub> is deduced to reflect the quantitative variation trend of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> and a design formula of the optimized N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SJ</sub> is presented. Furthermore, lateral SJ devices were fabricated according to the formula. The measured R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> values of the SJ devices are reduced by almost 35% when compared with the theoretical limit of the triple RESURF device in a voltage range of 100-400 V. The experiments also reveal that the measured net R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of the SJ region approaches the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on.sp</sub> ∝ V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1.03</sup> relationship.

Optimization and Experiments of Lateral Semi-Superjunction Device Based on Normalized Current-Carrying Capability

A lateral double diffused metal oxide semiconductor transistor with the semi-superjunction (semi-SJ LDMOS) is optimized based on the normalized current-carrying capability (CC) and experimentally realized in this letter. The device is fabricated based on an optimized equivalent substrate and the semi-SJ is introduced near the source. The semi-SJ increases the local doping concentration in the N regions meanwhile reduces the current path area and carrier mobility, resulting in the variation of CCs before and after the introduction of the semi-SJ. The normalized CC factor $\eta _{\text {C}}$ is proposed to evaluate this variation, with which the minimum specific on-resistance ${R} _ {\text {ON}, \text {sp}}$ is predicted by the condition of $\eta _{\text {C}}= {1}$ . The experiments of the semi-SJ LDMOS exhibit a minimum ${R} _ {\text {ON}, \text {sp}}$ of 25.5 $\text{m}\Omega \cdot $ cm2 under a breakdown voltage ${V} _{{\text {B}}}$ of 464.3 V. This represents a reduction in ${R} _ {\text {ON}, \text {sp}}$ by 37.7% when compared with the theoretical ${R} _ {\text {ON}, \text {sp}}$ of triple RESURF devices.

A new physical insight of RESURF effects based on gradual charge appointment concept for bulk silicon lateral power devices

A novel gradual charge appointment concept is proposed to provide a clear physical insight of RESURF effects in bulk silicon lateral power devices. Due to the expandable substrate depletion region in silicon power device, the Linearly Graded Approximation is unable to fully describe the 2-D coupling effects between vertical and lateral junction. In this paper, by defining a charge appointment line, the lateral abrupt junction behaves as an effective gradual junction, thus resulting in the wider depletion layer, lower field peak and higher breakdown voltage. Based on the hypothesis, a simple 1-D model is proposed to quantify the breakdown voltage of the bulk silicon RESURF device and formulize the surface electric field. To our knowledge, the proposed model is the first 1-D model for bulk silicon RESURF device which can accurately describe the surface field profiles under various applied voltages and structure parameters. Furthermore, we provide a new RESURF criterion to explore the sensitivity of the breakdown voltage to structure parameters. Fair agreements among the analytical, numerical and experimental results verify the availability of the proposed concept and model.

An Analytical Model of Triple RESURF Device with Linear P-layer Doping Profile

An analytical model of Triple RESURF device with linear P-layer doping profile is proposed in the paper. According to the analytical model and numerical simulation, the surface potential and electric field distributions of Single RESURF device, Double and Triple RESURF devices with linear-doped P-layer are investigated. The impacts of the P-layer doping profile on the breakdown voltage and specific on-resistance of Triple RESURF devices are discussed in detail, and the electric field modulation mechanism of the linear-doped P-layer is also described. In addition, the ideal P-layer doping profile, the maximum lateral breakdown voltage, and the optimal N-drift doping concentration are derived to guide the design of the Triple RESURF device. The analytical results are well supported by the simulation results, confirming the validity of the model presented here.

A 2-D Analytical Model of Soi High-Voltage Devices with Dual Conduction Layers

By solving 2-D Poisson’s equation, a new analytical model to calculate the electric field distribution of a SOI RESURF device with Dual Conduction Layers (Dual-CL) is firstly proposed. The proposed model is also available for the single RESURF and triple RESURF SOI devices without any modification. A matrix equation is developed for the determination of the lateral and vertical breakdown voltages, in which the influences of the N-top layer, P-top layer, and the N-drift region are all considered. A unified RESURF criterion of single RESURF, triple RESURF, and Dual-CL SOI devices is further derived for optimizing the structure parameters. A good agreement between the analytical results and the numerical results shows that the N-top layer and P-top layer have opposite impacts on the breakdown performance of Dual-CL SOI devices. In addition, an optimal trade-off between the breakdown voltage and the specific on-resistance for the triple RESURF and Dual-CL SOI devices is obtained due to the incorporation of the P-top layer.

A Novel RF SOI LDMOS with a Raised Drift Region

In this paper, we propose a novel RF SOI LDMOS with a raised drift region (RDR). Using the process simulation and numerical simulation, we investigate deeply on breakdown characteristics and frequency characteristics of this novel device. Compared with the conventional RESURF device, the breakdown voltage and cutoff frequency of the RDR device are increased by 25% and 21%, respectively. The work of this paper has theoretical and practical significations to the research of a new generation of deep sub-micron high-performance radio frequency SOI integrated circuits.

Analytical model for the surface electrical field distribution of double RESURF device with surface implanted P-top region

An analytical model for the surface electrical field distributions of double RESURF devices with Gaussian-doped P-top region is presented. Based on solvisng the 2-D Poisson equation, the model gives the closed form solutions of the surface potential and electrical field distribution as functions of the structure parameters and drain bias. The dependence of breakdown voltage on drift region length and thickness is calculated. An effectual way to get the optimum high-voltage devices is also proposed. All analytical results are well verified by simulation results obtained by MEDICI and previous experimental data, showing the validity of the presented model.

Analytical models for the surface potential and electrical field distribution of bulk-silicon RESURF devices

In this paper, two 2-D analytical models for the surface potential and electrical field distribution along the drift region of the bulk-silicon RESURF lateral-extended drain MOS (LEDMOS) have been presented, which can be applied in the off- and on-states. The models give an approximate but explicit influence on surface potential and electrical field distributions in terms of the structure and fabricated process parameters, such as the length of the poly gate-field-plate, the implanted dose of the drift region, the diffusion time of the drift region and the substrate doping concentration etc. An effectual way to gain the optimum high-voltage device is also proposed. The analytical results are well supported by the simulation results obtained by Medici.

Characterization of vertical RESURF diodes using scanning probe microscopy

Recently, a new process to manufacture vertical RESURF devices was proposed. By using trench etching and subsequent vapor phase doping the alternating p–n junctions in the drift region of such a diode can be formed. For the characterization of these diodes, a two-dimensional (2D) characterization technique is necessary. The use of atomic force microscopy based techniques, such as scanning capacitance microscopy (SCM) and Nanopotentiometry (NP) are nowadays promising tools for the 2D dopant profiling of semiconductor devices. In a first part SCM is used to image the 2D carrier profile of the device, more specific the boron doped layer at the trench sidewalls. A uniform profile is observed along the trench sidewalls. The thickness of the alternating regions in the drift region can be determined with high resolution. Also a semi-quantitative analysis is done with SCM. The concentration in the p-type layer is estimated to be between 1×10 17 and 4×10 18 at. cm −3. In a second part NP is used to image the evolution of the depletion region within the drift region, when the diode is under reverse bias. For higher voltages the depletion region in the drift region expands. Also a comparison between the experimental results and simulations for NP is presented.

Analytical modelling for the RESURF effect in JI and SOI power devices

The authors present a review and assessment of state-of-the-art analytical models which describe the breakdown behaviour of JI and SOI RESURF power devices. The results are compared with numerical values, and a short evaluation of strengths and weaknesses specific to each model is given. A new modelling concept for the breakdown regime in RESURF power structures is introduced, and the results are assessed against numerical values. The same technique can be used to derive the breakdown voltage of RESURF devices fabricated in JI and SOI technologies, and is potentially useful for non-standard technologies, such as linearly graded SOI, partial SOI and 3-D RESURF. The model provides accurate description for punch-through, non-punch-through and volume breakdown.

An analytical model for interaction of SIPOS layer with underlying silicon of SOI RESURF devices

An analytical model for interaction of semi-insulating polycrystalline silicon (SIPOS) layer with underlying silicon of SOI RESURF devices is presented which allows a clear picture of the potentials in the two regions coupled through the device parameters including the interface oxide thickness between the regions. The improvement in the breakdown voltage due to the presence of SIPOS layer is demonstrated, numerical simulations are shown to support the analytical model.

Modelling and improving the on-resistance of LDMOS RESURF devices

We present in this paper some techniques to decrease the value of the drift region on-resistance of a lateral DMOS transistor (LDMOS). We first evaluate the technique using a shallow implanted layer between the channel and the drain of the transistor, whose doping is somewhat higher than the background doping level. Dose and energy should be carefully calibrated in order to ensure the largest on-resistance improvement but a good trade-off with the breakdown voltage is difficult. Secondly, we assess the on-resistance improvement achievable using a semi-resistive layer deposited between the gate and drain metals above the oxide layer. This will enhance the accumulated drift area and consequently decrease the on-resistance. The achievable improvement is less than for the surface doping technique. We propose to use both techniques to obtain the best on-resistance improvement/breakdown voltage trade-off. Surface doping will be employed to decrease the on-resistance and the semi-resistive layer will keep the breakdown voltage to its optimal value. We assess and demonstrate, with both analytical and numerical analyses, that large improvements can be achieved with these techniques without degrading the voltage handling capacity of the device. The on-resistance can be lowered by 40 to 66%. Experimental LDMOS transistors will be presented which exhibit good agreement with the theoretical predictions.

OBIC Measurement of High Voltage RESURF Devices Having SIPOS Passivation

OBIC Measurement of High Voltage RESURF Devices Having SIPOS Passivation

Modeling and Optimization of Lateral High Voltage IC Devices to Minimize 3-D Effects

High Voltage blocking capability of the RESURF or Lateral Charge Control (LCC) devices are strongly junction curvature dependent. A new charge model has been developed to translate 3-D curvature effect into 2-d plane. Existing 2-D computer program in conjunction with this new model has been utilized to model and optimize the LCC devices for high voltage 9C's. Theoretical predictions of this model are within 10% of the measured results.

Thin layer high-voltage junction FET (resurf JFET)

The application of Resurf layers [1] especially in relation to high-voltage silicon JFETs is described. Because the breakdown voltage in Resurf devices is in principle determined by the high-ohmic substrate, the possibility is opened to make high-voltage JFETs in very thin, relative highly doped top layers. By making use of a profiled instead of a constant impurity doping concentration in these layers, the drain saturation current can be enlarged considerably while the same channel thickness is maintained.