Resistive Switching Memory Arrays Research Articles

Multifunctional double active layers formed with electrochemically controlled nanoparticle dispersion for resistive switching memory arrays

Expanding resistive random-access memory (RRAM) from a single device to an array requires a selector to suppress the sneak path and an external device to control the compliance current. Thus, a unique crossbar array that can be independently driven through the novel design of a multilayer RRAM structure with intelligently controlled Cu2O consisting of nanoparticles embedded in the amorphous matrix (ANPs) is proposed. The ANPs–Cu2O active layers are prepared by electrodeposition, and the negative shift of the deposition potential induces a higher density and smaller size of the nanoparticles. The ANPs–Cu2O films show different set voltages and extremely uniform reset voltages, and thus a functional double active layer (DAL) structure consisting of two ANPs–Cu2O layers with different set voltages is proposed. The electrochemically fabricated VCu-controlled DALs effectively protected the reverse current from the self-rectifying characteristics of a large forward/reverse current ratio, thus realizing selector-less RRAMs. In addition, the soft-breakdown showing filament formation in the upper layer reveals the saturation current step acting as a self-compliance current without the assistance of transistors. Finally, a 4 × 4 crossbar DAL RRAM array with transistor-less self-rectification is demonstrated, which shows excellent memory performance and endurance without interfering with adjacent cells.

Impact of Relaxation on the Performance of GeSe True Random Number Generator Based on Ovonic Threshold Switching

Volatile Ovonic threshold switching (OTS) are promising not only as the selector in crossbar resistive switching memory arrays, but also as true random number generators (TRNG) by utilizing its probabilistic switching characteristics. However, investigation on the reliability of OTS-based TRNG is still lacking, which hinders its practical application. Previously, we found that switching probability is dependent on the pulse amplitude and width. In this work, we report that relaxation which happens during the time interval between pulses can also cause switching probability drift. Optimizing the bit-generation waveform and modulating the pulse conditions could provide a practical solution, in addition to the impact of external bias and temperature. This work provides useful guidance for the practical design and operation of OTS-based TRNGs.

Multilevel switching memristor by compliance current adjustment for off-chip training of neuromorphic system

Multilevel operation is one of the most essential properties for synaptic devices to realize hardware artificial neural networks. Compliance current (Icc) adjustment is a multilevel programming method that can be utilized for a large-scale one-transistor and one-resistor (1T1R) array. It protects the devices from permanent breakdown by regulating abrupt switching. However, according to the reported literature so far, the number of conductance states in the Icc control method is insufficient to implement off-chip-trained neuromorphic systems. Therefore, we experimentally explore the feasibility of a larger number of conductance states using the Icc control method. We fabricated an Al2O3/TiOx-based resistive switching memory array, observed the conductance change while increasing Icc during set operations, and 64-level conductance states were statistically demonstrated. Furthermore, we verified that the 64-level states showed recognition performance close to that of a software-based neural network through off-chip learning of the convolutional neural network (CNN) structure. The fabricated synaptic device array with the Icc-control programming method is expected to contribute to the development of hardware neural network by reducing the information loss in the transfer process.

Te-based chalcogenide materials for selector applications

The implementation of dense, one-selector one-resistor (1S1R), resistive switching memory arrays, can be achieved with an appropriate selector for correct information storage and retrieval. Ovonic threshold switches (OTS) based on chalcogenide materials are a strong candidate, but their low thermal stability is one of the key factors that prevents rapid adoption by emerging resistive switching memory technologies. A previously developed map for phase change materials is expanded and improved for OTS materials. Selected materials from different areas of the map, belonging to binary Ge-Te and Si-Te systems, are explored. Several routes, including Si doping and reduction of Te amount, are used to increase the crystallization temperature. Selector devices, with areas as small as 55 × 55 nm2, were electrically assessed. Sub-threshold conduction models, based on Poole-Frenkel conduction mechanism, are applied to fresh samples in order to extract as-processed material parameters, such as trap height and density of defects, tailoring of which could be an important element for designing a suitable OTS material. Finally, a glass transition temperature estimation model is applied to Te-based materials in order to predict materials that might have the required thermal stability. A lower average number of p-electrons is correlated with a good thermal stability.

Comprehensive Study of Write Operation Scheme in Multi-Level Resistive Switching Memory Array

Comprehensive Study of Write Operation Scheme in Multi-Level Resistive Switching Memory Array

Highly-Ordered 3D Vertical Resistive Switching Memory Arrays with Ultralow Power Consumption and Ultrahigh Density.

Resistive switching random access memories (RRAM) have attracted great scientific and industrial attention for next generation data storage because of their advantages of nonvolatile properties, high density, low power consumption, fast writing/erasing speed, good endurance, and simple and small operation system. Here, by using a template-assisted technique, we demonstrate a three-dimensional highly ordered vertical RRAM device array with density as high as that of the nanopores of the template (10(8)-10(9) cm(-2)), which can also be fabricated in large area. The high crystallinity of the materials, the large contact area and the intimate semiconductor/electrode interface (3 nm interfacial layer) make the ultralow voltage operation (millivolt magnitude) and ultralow power consumption (picowatt) possible. Our procedure for fabrication of the nanodevice arrays in large area can be used for producing many other different materials and such three-dimensional electronic device arrays with the capability to adjust the device densities can be extended to other applications of the next generation nanodevice technology.

A new analytical electro-thermal model in 3D resistive switching memory arrays

Resistive switching memory (RRAM) with three-dimensional (3D) integration is one of the most effective methods to satisfy the requirement of ultra-high density and ultra-large data storage. With the increase of the integration density of 3D RRAM, Joule heating effect and thermal crosstalk of the RRAM device will seriously affect the stability, reliability and life of RRAM device. Therefore, the biggest challenge for 3D RRAM is how to solve the problem of the thermal effect. Otherwise, the thermal effect will be particularly prominent as the feature size of RRAM device is ceaselessly decreased. Especially with the improving of the storage cell densities and hence the decreasing of the distance between adjacent cells, the thermal crosstalk from the adjacent cells will seriously restrict the development and application of 3D integrated RRAM. In this work, we present a new electro-thermal compact model for 3D RRAM arrays. The proposed model is based on the electro-thermal analogy which can couple thermal network to its electrical schematic. The comparison between the compact model simulation results and numerical simulation shows a good accuracy. This proposed model can be used to predict temperature distribution and analyze thermal crosstalk in 3D RRAM arrays. Our work will provide a reliable technical support for the late circuit design and practical application, and lay the foundation for the realization of the high-density 3D integration RRAM.

Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array

Disturbance characteristics of cross-point resistive random access memory (RRAM) arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.

Fully Si compatible SiN resistive switching memory with large self-rectification ratio

In this letter, we report unique unipolar resistive switching memory behaviors in the Ni/Si3N4/p-Si structure by controlling the impurity concentration of Si bottom electrode. It is found that we can decrease the reset current drastically by reducing dopant concentration by reducing dopant concentration, which helps low-power operation in the high density resistive switching memory array. Also, the samples with high impurity concentration exhibited ohmic conduction in the low-resistance state (LRS) while those with low dopant concentration below 1018 cm−3 showed a remarkable self-rectifying behavior. The nonlinear metal-insulator-semiconductor (MIS) diode characteristics in the samples with low doping concentration (∼1018 cm−3) are explained by the formation of Schottky barrier at the metal and semiconductor interface. As a result, we demonstrate high rectification ratio (>105) between forward and reverse currents along with the robust nonvolatile properties including endurance cycles and retention from the devices with large self-rectification ratio. The high self-rectifying characteristics of Si3N4-based RRAM cell would be one of the most virtuous merits in the high-density crossbar array.

Flexible one diode–one resistor resistive switching memory arrays on plastic substrates

Flexible one diode–one resistor resistive random access memory (RRAM) with 8 × 8 arrays composed of high-performance silicon diodes and a resistive change material for fully functional flexible memory operation.