Resistive Random Access Memory Resistance Research Articles

Performance degradation and I–V model of TiO2-film-based resistive switching memory under proton irradiation

The performance degradation of a TiO2-film-based RRAM (resistive random access memory) is investigated in a proton irradiation experiment with an energy of 25 MeV. The results reveal that the fabricated Au/TiO2 film/Ti devices exhibit typical I–V of bipolar resistive switching behavior under an irradiation of 1 × 1011 protons/cm2. The low-resistance state (LRS) resistance remains nearly constant, but the high-resistance state (HRS) resistance decreases with an increasing proton fluence. The value of the HRS resistance decreases by approximately one order of magnitude when the value of proton fluence reaches 1 × 1011 protons/cm2. Moreover, the SET voltage decreases with a decreasing proton fluence, while the RESET voltage remains almost constant. Material characterization via x-ray photoelectron spectroscopy demonstrates that the decrease in SET voltage and HRS resistance is mainly caused by radiation-induced oxygen vacancies and non-lattice oxygen. Based on the Voltage Threshold Adaptive Memristor model, a mathematical model of the I–V curve which demonstrates the variation in the RRAM resistance and voltage as a function of proton irradiation is constructed. The simulation results conformed to the experimental results under different proton fluences. Our results form a fundamental guide for the study of radiation performance degradation and radiation hardening of the RRAM with oxygen vacancy conducting filament.

Study on ion dynamics of hafnium oxide RRAM by electrode thermal effect

Resistive random access memory (RRAM) has become one of the representatives of the next generation of nonvolatile memory because of its excellent performance, and the data reading function is caused by the growth and fracture of the conductive filament (CF) in the switch layer. Therefore, the study of the thermal properties of materials on the conductive mechanism is a step that cannot be ignored. In this paper, a numerical model of filament dissolution caused by the coupling effect of Joule heat and electric field in resistance elements is established. The influence of the thermal field on the electric field and ion mobility during device setup and reset is explained by solving partial differential equations. On this basis, the importance of electrode parameters for resistive switching behavior is emphasized. The results show that the best performance can be obtained at 298 K when TiN is selected as the top electrode material of the equipment. This work has deepened the understanding of RRAM resistance switch characteristics and has guiding significance for selecting memristor materials and promoting its industrialization process.

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References

Resistive random access memory (RRAM)-based compute-in-memory (CIM) has shown great potential for accelerating deep neural network (DNN) inference. However, device characteristics, such as low-resistance values, susceptibility to drift, and single-level cells, may limit the capabilities of RRAM-based CIM. In addition, prior works generally used the off-chip write-verify scheme to tighten RRAM resistance distributions and used off-chip analog-to-digital converter (ADC) references for fine-tuning partial sum quantization. Although off-chip techniques are viable for testing purposes, they may be unsuitable for practical applications. In this work, we present an RRAM-CIM macro to accelerate DNN inference. The chip features: 1) multi-level cell (MLC) RRAM for improving compute performance and density; 2) sparsity-aware input control to leverage the high activation sparsity in DNN models; 3) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift under stress; and 4) on-chip ADC reference generation that provides column-wise tunability and stability with varying temperatures to guarantee the CIFAR-10 accuracy of 85.8% at 120 °C. The design is fabricated in TSMC 40-nm process with embedded RRAM technology and achieves a macro-level peak performance of 97.8 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 44.5 TOPS/W for multiply-and-accumulate (MAC) operations on VGG-8 network with ternary weights.

Elucidating Postprogramming Relaxation in Multilevel Cell‐Resistive Random Access Memory by Means of Experimental and Kinetic Monte Carlo Simulation Data

This work explores the phenomenon of HfO2 resistive random access memory (RRAM) postprogramming resistance relaxation using experimental data and kinetic Monte Carlo (KMC) physical simulation. This issue has become an important limitation for multilevel cell (MLC) applications. The physical KMC simulation replicates the RRAM cell‐to‐cell intrinsic resistance variability due to the conductive filament (CF) morphology fluctuations and the weak correlation between the number of oxygen vacancies and the resulting resistance. It furthermore accurately simulates the vacancies’ microscopic dynamics within the CF that are responsible for the RRAM resistance relaxation. A link between programming current, CF size/configuration, and relaxation amplitude is clarified and shows the ensuing benefits and limitations of smart programming techniques (read &amp; verify) for MLC applications. Coupled with experimental data obtained on HfO2‐based RRAM arrays, this simulation paves the way to a better understanding of the physics at stake in the RRAM relaxation process and provides guidelines to potential technological solutions for MLC reliability prediction.

Early-Stage Fluctuation in Low-Power Analog Resistive Memory: Impacts on Neural Network and Mitigation Approach

In this letter, a new reliability phenomenon, named early-stage resistance fluctuation (ERF), in analog resistive random-access memory (RRAM) devices and its impact on the neuromorphic computing are investigated. ERF is found to be a non-negligible random fluctuation behavior of RRAM resistance within ~10,000s after verification due to stochastic migration of vacancies. As a result, ERF can induce weight noise in RRAM-based neural network even with write-verify operation and cause a significant (~42%) drop of recognition accuracy on the MNIST dataset recognition tasks. An approach incorporating automatic early-stop and dropout during training is proposed to reduce the impacts of ERF. Results show that the recognition accuracy with ERF can be improved from 58% to 96% after adopting the proposed optimization method.

Exploring the Impact of Variability in Resistance Distributions of RRAM on the Prediction Accuracy of Deep Learning Neural Networks

In this work, we explore the use of the resistive random access memory (RRAM) device as a synapse for mimicking the trained weights linking neurons in a deep learning neural network (DNN) (AlexNet). The RRAM devices were fabricated in-house and subjected to 1000 bipolar read-write cycles to measure the resistances recorded for Logic-0 and Logic-1 (we demonstrate the feasibility of achieving eight discrete resistance states in the same device depending on the RESET stop voltage). DNN simulations have been performed to compare the relative error between the output of AlexNet Layer 1 (Convolution) implemented with the standard backpropagation (BP) algorithm trained weights versus the weights that are encoded using the measured resistance distributions from RRAM. The IMAGENET dataset is used for classification purpose here. We focus only on the Layer 1 weights in the AlexNet framework with 11 × 11 × 96 filters values coded into a binary floating point and substituted with the RRAM resistance values corresponding to Logic-0 and Logic-1. The impact of variability in the resistance states of RRAM for the low and high resistance states on the accuracy of image classification is studied by formulating a look-up table (LUT) for the RRAM (from measured I-V data) and comparing the convolution computation output of AlexNet Layer 1 with the standard outputs from the BP-based pre-trained weights. This is one of the first studies dedicated to exploring the impact of RRAM device resistance variability on the prediction accuracy of a convolutional neural network (CNN) on an AlexNet platform through a framework that requires limited actual device switching test data.

NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion

Traditional analog-to-digital converters (ADCs) employ dedicated analog and mixed-signal (AMS) circuits, requiring time-consuming manual design process. They also exhibit limited configurability to support diverse quantization schemes on the same circuitry. In this paper, we propose NeuADC-an automated design approach to synthesizing an analog-to-digital (A/D) interface that can approximate the desirable quantization function using a neural network (NN) with a single hidden layer. We leverage the mixed-signal resistive random-access memory (RRAM) crossbar architecture to design a novel dual-path configuration for the implementation of the basic NN operations at the circuit level. We exploit alternative bits encoding scheme to the conventional binary encoding to improve the training accuracy. Our method incorporates nonidealities at the device and circuit level into the training process to ensure NeuADC's robustness against variations of process, supply voltage, and temperature (PVT). Results obtained from SPICE simulation based on RRAM and standard 130-nm CMOS technology suggest that not only can NeuADC deliver promising performance compared to the state-of-the-art ADCs and other emerging converter designs across comprehensive design metrics, but it can also intrinsically support multiple configurable quantization schemes using the same hardware substrate, paving ways for future adaptable application-driven signal conversion. Our systematic evaluations on the proposed NeuADC framework also quantify the impacts on the ADC quantization quality from hidden neuron sizes, RRAM resistance imprecision, and PVT variations, and reveal the design tradeoff between speed, power, and area in a NeuADC circuit.

A Novel RRAM Based PUF for Anti-Machine Learning Attack and High Reliability

Due to the unique response mechanism, physical unclonable function (PUF) has been extensively studied as a hardware security primitive. And compared to other PUFs, the resistive random access memory (RRAM) based PUF has more flexibility with the change of conductive filaments. In this work, we propose an exclusive or (XOR) strong PUF based on the 1 Kbit 1-transistor-1-resistor (1T1R) arrays, and unlike the traditional RRAM based strong PUF, the XOR PUF has a stronger anti-machine learning attack ability in our experiments. The reliability of XOR RRAM PUF is determined by the read instability, thermal dependence of RRAM resistance, and aging. We used a split current distribution scheme to make the reliability of XOR PUF significantly improved. After baking for 50 h at a high temperature of 150°C, the intra-chip Hamming distance (Intra-HD) only increased from 0 to 4.5%. The inter-chip Hamming distance (Inter-HD) and uniformity are close to 50% (ideally). And it is proven through the NIST test that XOR PUF has a high uniqueness.

Resistive RAMs as analog trimming elements

This work investigates the use of Resistive Random Access Memory (RRAM) as an analog trimming device. The analog storage feature of the RRAM cell is evaluated and the ability of the RRAM to hold several resistance states is exploited to propose analog trim elements. To modulate the memory cell resistance, a series of short programming pulses are applied across the RRAM cell allowing a fine calibration of the RRAM resistance. The RRAM non volatility feature makes the analog device powers up already calibrated for the system in which the analog trimmed structure is embedded. To validate the concept, a test structure consisting of a voltage reference is evaluated.

Communication—Effect of a Self-Limited Reset Operation on the Reset Breakdown Characteristics of a Monolithically Integrated 1T1R RRAM

The reset breakdown of resistive random access memory (RRAM) significantly degrades device endurance. We suppressed reset breakdown by optimizing the reset operation in an HfO2-based 1T1R RRAM device. The effective gate-to-source voltage VGSeff is reduced by increasing the RRAM resistance during the reset operation. By applying the optimum VGS, we can both guarantee a sufficient reset current and suppress reset breakdown. The experimental results confirmed improved endurance characteristics without a degraded resistance ratio.

Utilizing the Variability of Resistive Random Access Memory to Implement Reconfigurable Physical Unclonable Functions

The stochastic switching mechanism and intrinsic variability of resistive random access memory (RRAM) present severe challenges for memory applications, which, however, may be utilized to implement the physical unclonable function (PUF) for hardware security. A PUF based on RRAM resistance variability is proposed in this letter. Unlike PUFs based on manufacturing variation, this proposal exploits an intrinsic variability in physical mechanisms with reconfigurability. Key characteristics of the PUF design are assessed by simulation using measured RRAM properties and device model. Truly random variation of RRAM resistance is critical for PUF uniqueness (or unclonability). The reliability (or robustness) of the proposed PUF is affected by temperature and voltage dependence of RRAM resistance as well as retention characteristics. Large separation between inter-chip and intra-chip Hamming distance as the measure of uniqueness and reliability confirms the feasibility of the PUF proposal.

Dynamic Modeling of Radiation-Induced State Changes in &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\hbox {HfO}_2}/\hbox {Hf}$&lt;/tex&gt;&lt;/formula&gt; 1T1R RRAM

Single and multiple-event upsets in ${\hbox {HfO}_2}/\hbox {Hf}$ one transistor, one resistor (1T1R) resistive random access memory (RRAM) structures are modeled dynamically using 3-D technology computer-aided design (TCAD) simulations. A dynamic single-event compact model is presented that allows direct correlation of the ion-generated voltage transient across the RRAM and the change in RRAM resistance. Experiments and modeling demonstrate an exponential relationship between the susceptibility of the RRAM and the applied voltage. Two implementations of the model are also presented including hardening voltage-susceptible resistive memory technologies and the impact of highly scaled access transistors.

Single- and Multiple-Event Induced Upsets in &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\rm HfO}_2/{\rm Hf}$&lt;/tex&gt;&lt;/formula&gt; 1T1R RRAM

Single-event upsets in 1T1R Resistive Random Access Memory (RRAM) structures are experimentally demonstrated by generating current transients in the access transistors of the memory cells. The relationship between the single-event upset threshold of the RRAM and the applied voltage is exponential, which is verified using TPA laser analysis and heavy-ion irradiation. Multiple-Event Upsets (MEUs) also occur, where individual ions incrementally change the RRAM's resistance until their cumulative effect causes an upset. Single-event models are presented that allow direct correlation of the voltage across the RRAM, caused by the ion-generated current transient, and the change in RRAM resistance. The RRAM is vulnerable only in the high resistance state, when a voltage capable of writing to the cell is applied to the bit line. This is approximately 0.5% of the memory element's operation time, leading to relatively low projected upset rates.