Resistive Feedback Research Articles

A CMOS Optoelectronic Transimpedance Amplifier Using Concurrent Automatic Gain Control for LiDAR Sensors

This paper presents a novel optoelectronic transimpedance amplifier (OTA) for short-range LiDAR sensors used in 180 nm CMOS technology, which consists of a main transimpedance amplifier (m-TIA) with an on-chip P+/N-well/Deep N-well avalanche photodiode (P+/NW/DNW APD) and a replica TIA with another on-chip APD, not only to acquire circuit symmetry but to also obtain concurrent automatic gain control (AGC) function within a narrow single pulse-width duration. In particular, for concurrent AGC operations, 3-bit PMOS switches with series resistors are added in parallel with the passive feedback resistor in the m-TIA. Then, the PMOS switches can be turned on or off in accordance with the DC output voltage amplitudes of the replica TIA. The post-layout simulations reveal that the OTA extends the dynamic range up to 74.8 dB (i.e., 1 µApp~5.5 mApp) and achieves a 67 dBΩ transimpedance gain, an 830 MHz bandwidth, a 16 pA/√Hz noise current spectral density, a −31 dBm optical sensitivity for a 10−12 bit error rate, and a 6 mW power dissipation from a single 1.8 V supply. The chip occupies a core area of 200 × 120 µm2.

INCAPE23-Design of Class E CMOS Power Amplifier with Integrated Active Inductor for 5G Applications

This paper presents a design of class E power amplifier (PA) with integrated active inductor for 5G applications. A high Q-factor active inductor (AI) is proposed utilizing CMOS 0.18-µm technology. A Gyrator-C based is employed to realize an active inductor with a double cascode resistive feedback configuration. The biasing voltage of 1.21 V, current source of 0.5 mA and supply voltage of 2.5 V is used. In order to obtain high efficiency, the proposed AI is implemented in a class E power amplifier by replacing on of the spiral inductors. According to the simulation results, the proposed AI can reach a high Q-factor of 50,000 and an inductance of 2.03 nH at 3.5 GHz. The power added efficiency (PAE) of CMOS class E PA with integrated AI, according to simulation result, is 72 % at 3.5 GHz. The intended PA's PAE was dramatically raised by the class E AI that was built.

A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier

A current-reused folded cascode operational transconductance amplifier (OTA) using a local positive feedback (LPFB) technique has been proposed in previous literature, which does not achieve maximum unity gain-bandwidth (GBW). Besides, the stability of LPFB in the LPFB-OTA is limited by local common mode feedback (LCMFB) resistors. Based on the analysis, a local positive feedback loop-reused (LPFBR) technique is proposed to improve the performance of conventional LPFB OTA. For a fair comparison, both conventional and proposed OTAs working at saturation region are designed and simulated in SMIC 0.18μm process. The simulated results demonstrate that the proposed LPFBR-OTA has almost 10.5 times the bandwidth and maintains stability compared to that of the conventional LPFB-OTA under the condition that LCMFB resistors are increased by a factor of 10.

Robust Pixel Design Methodologies for a Vertical Avalanche Photodiode (VAPD)-Based CMOS Image Sensor.

We present robust pixel design methodologies for a vertical avalanche photodiode-based CMOS image sensor, taking account of three critical practical factors: (i) "guard-ring-free" pixel isolation layout, (ii) device characteristics "insensitive" to applied voltage and temperature, and (iii) stable operation subject to intense light exposure. The "guard-ring-free" pixel design is established by resolving the tradeoff relationship between electric field concentration and pixel isolation. The effectiveness of the optimization strategy is validated both by simulation and experiment. To realize insensitivity to voltage and temperature variations, a global feedback resistor is shown to effectively suppress variations in device characteristics such as photon detection efficiency and dark count rate. An in-pixel overflow transistor is also introduced to enhance the resistance to strong illumination. The robustness of the fabricated VAPD-CIS is verified by characterization of 122 different chips and through a high-temperature and intense-light-illumination operation test with 5 chips, conducted at 125 °C for 1000 h subject to 940 nm light exposure equivalent to 10 kLux.

A low-complexity and high-frequency ASIC transceiver for an ultrasound imaging system.

This article presents a high-frequency application-specific integrated circuit (ASIC) transceiver for an ultrasound imaging system designed with a focus on low complexity. To simplify the design, it employs a conventional Class-D power amplifier structure for the transmitter (TX) and a resistive feedback transimpedance amplifier (TIA), which consists of a common-source amplifier followed by a source follower for the receiver (RX). Through careful optimization, the RX achieves a measured transimpedance gain of 90 dBΩ and an input-referred noise of 5.6 pA/√Hz at 30MHz while maintaining a wide bandwidth of up to 30MHz for both the TX and RX. The power consumption of the TX and RX is measured to be 7.767 mW and 2.5 mW, respectively. Further acoustic performance, assessed using an annular capacitive micromachined ultrasonic transducer (CMUT), showed a 1.78kPa peak pressure from a 20V pulser and confirmed the full bandwidth compatibility of the CMUT's bandwidth. The ASIC transceiver has been fabricated using a 0.18μm HV bipolar-CMOS-DMOS (BCD) process.

Innovative techniques for achieving flat response in a dual-resonance ultra-wideband low-noise amplifier

This paper introduces a two-stage ultra-wideband low-noise amplifier (UWB-LNA) intended to be used in wireless communication systems. The architecture uses a novel double-resonance load network in the first stage and resistive shunt feedback in the second stage to achieve wide bandwidth with a flat response. A common gate stage at the input port seeks to present a high-impedance load to the single resonant network, while concurrently shunt negative feedback, source degeneration, and cascoded feedback schemes are used to improve performance. In this respect, the cascoded feedback provides flat gain across a wide bandwidth, while the source degeneration helps in impedance matching. Post-layout foot-print for the UWB-LNA designed and simulated using Cadence Virtuoso 180nm technology is 0.532 mm2 with an operating frequency 3.1–10.6 GHz incorporated. Operating on a 1.8 V supply voltage, it consumes 6 mW of power. The amplifier achieves a maximum gain of 18.75 dB, maintaining a flat low noise figure of 3.15 dB across frequencies ranging from 3.1 to 10.6 GHz. Stability analysis using the Roulettes test confirms the reliability of the proposed LNA, with Kf > 1 and Δ < 1.

A low noise capacitance to voltage readout circuit based on active feedback charge sensitive amplifier for micro-gyro.

Trans-impedance amplifier (TIA) based capacitance-voltage (C-V) readout circuits are widely used in micro-machined gyroscopes' control system. In this work, the noise performance of a TIA and charge sensitive amplifier (CSA) based C-V readout circuit is analyzed in detail. The theoretical derivation and simulation experiments carried out in this paper show that the thermal noise of high value feedback resistors in TIA dominates the output noise of the circuit, while a CSA-based readout circuit can overcome this shortcoming. Then, a CSA-based C-V readout circuit is designed with a 1.8V transistor on a 180nm complementary metal-oxide-semiconductor. This C-V-based readout circuit occupies an area of 0.039 mm2, which is smaller than the area of a 0603 package resistor. When 1V bias voltage (Vb) is added to the capacitors under test, the tested C-V gain of this circuit is as high as 225 dB, and the tested output noise of the circuit is less than 150 nV/Hz. Finally, the fabricated chip achieved a resolution of 840 zF/Hz at Vb as low as 1V. This CSA-based C-V readout circuit has more advantages in terms of noise and area over the TIA circuit and is more suitable for integration into the interface integrated circuit for micro-gyroscopes.

A 60 dB gain range programmable gain current amplifier for ultrasound sensing

This article presents a programmable gain current amplifier (CA) for ultrasound sensing applications. The design proposed consists of a current divider and a close-loop current amplifier. The CA utilizes switches to adjust the resistance of the shunt resistors and feedback resistors to achieve variable gain, thus realizing the time gain compensation (TGC) function. The proposed CA implemented in 180-nm BCD technology occupies an active area of 0.059 mm2. Measurement results show that the CA achieves a maximum gain of 36.6 dB and a gain range of 60 dB. The average input-referred noise spectral density is 0.32 pA/√Hz at maximum gain condition while consuming a power of 1.07 mW.

A multichannel thermal bubble-actuated impedance flow cytometer with on-chip TIA based on CMOS-MEMS

Electrochemical impedance spectroscopy (EIS) flow cytometry offers the advantages of speed, affordability, and portability in cell analysis and cytometry applications. However, the integration challenges of microfluidic and EIS read-out circuits hinder the downsizing of cytometry devices. To address this, we developed a thermal-bubble-driven impedance flow cytometric application-specific integrated circuit (ASIC). The thermal-bubble micropump avoids external piping and equipment, enabling high-throughput designs. With a total of 36 cell counting channels, each measuring 884 × 220 μm2, the chip significantly enhances the throughput of flow cytometers. Each cell counting channel incorporates a differential trans-impedance amplifier (TIA) to amplify weak biosensing signals. By eliminating the parasitic parameters created at the complementary metal-oxide-semiconductor transistor (CMOS)-micro-electromechanical systems (MEMS) interface, the counting accuracy can be increased. The on-chip TIA can adjust feedback resistance from 5 to 60 kΩ to accommodate solutions with different impedances. The chip effectively classifies particles of varying sizes, demonstrated by the average peak voltages of 0.0529 and 0.4510 mV for 7 and 14 μm polystyrene beads, respectively. Moreover, the counting accuracies of the chip for polystyrene beads and MSTO-211H cells are both greater than 97.6%. The chip exhibits potential for impedance flow cytometer at low cost, high-throughput, and miniaturization for the application of point-of-care diagnostics.

A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology

In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency.

Ultra-wideband high gain low group delay variation amplifier for phased-array radar system

This paper describes a ultra-wideband (UWB) three-stage cascaded high gain amplifier with low group delay variation for phased-array radar system. The shunt inductor at the input not only provides an electrostatic discharge (ESD) path to ground, but also introduces a new notch for S11, thus extending the matching bandwidth. Staggered tuning of load impedance peaks at each stage facilitates a balance between flat gain and low group delay variation. The output stage further enhances the overall gain while reinforcing bandwidth and stability through resistive feedback, and employs an adaptive bias circuit for linearity improvement. Implemented in SMIC 40-nm CMOS technology, the proposed amplifier achieves good input impedance matching, flat gain and low group delay variation of ±73.5 ps over 4.7–16 GHz. The whole power consumption is 198.3 mW and the output 1 dB compression point (OP1dB) is greater than 9 dBm. After careful design, the chip size is 0.64 mm2.

Ultra-wideband low noise amplifier using resistive feedback and current reause

Ultra-wideband low noise amplifier using resistive feedback and current reause

Comprehensive Noise Modeling of Piezoelectric Charge Accelerometer with Signal Conditioning Circuit.

This paper reports on noise modeling of a piezoelectric charge accelerometer with a signal conditioning circuit. The charge output is converted into voltage and amplified using a JFET operational amplifier that has high input resistance and low noise. The noise sources in the whole system include electrical and mechanical thermal noises of the accelerometer, thermal noises of resistors, and voltage and current noises of the operational amplifier. Noise gain of each source is derived from small signal circuit analysis. It is found that the feedback resistor of the operational amplifier is a major source of noise in low frequencies, whereas electrical thermal noise of the accelerometer dominates the rest of spectrum. This method can be used to pair a highly sensitive sensor with a single JFET operational amplifier instead of a multi-stage signal conditioning circuit.

A Highly Integrated C-Band Feedback Resistor Transceiver Front-End Based on Inductive Resonance and Bandwidth Expansion Techniques.

This paper presents a highly integrated C-band RF transceiver front-end design consisting of two Single Pole Double Throw (SPDT) transmit/receive (T/R) switches, a Low Noise Amplifier (LNA), and a Power Amplifier (PA) for Ultra-Wideband (UWB) positioning system applications. When fabricated using a 0.25 μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process, the switch is optimized for system isolation and stability using inductive resonance techniques. The transceiver front-end achieves overall bandwidth expansion as well as the flat noise in receive mode using the bandwidth expansion technique. The results show that the front-end modules (FEM) have a typical gain of 22 dB in transmit mode, 18 dB in receive mode, and 2 dB noise in the 4.5-8 GHz band, with a chip area of 1.56 × 1.46 mm2. Based on the available literature, it is known that the proposed circuit is the most highly integrated C-band RF transceiver front-end design for UWB applications in the same process.

A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor

Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals with low-level amplitudes (from tens of μV to tens of mV) and broadband low-frequency ranges (from sub-Hz to several hundred Hz). Possessing a high input impedance, an instrumentation amplifier (IA) accurately amplifies signals with low amplitude and low frequency, making it suitable for AFE circuits. This work demonstrates a capacitively coupled IA whose feedback resistance is realized by the proposed hybrid resistor, consisting of a switched-capacitor low-pass filter, a switched-capacitor resistor, and a continuous-time low-pass filter. The capacitively coupled IA achieves tera-ohm (TΩ) resistance and is insensitive to process, voltage, and temperature (PVT) variations. The simulation results show that the proposed IA illustrates a high-pass corner of 73.9 mHz, and the change of its high-pass corner with temperature is 0.05 mHz/°C. With the variation in the PVT corners, the difference between the maximum and minimum values of the high-pass corner of the proposed capacitively coupled IA is only 0.06 Hz. The design was implemented in a 130 nm standard CMOS process. The AFE with the proposed capacitively coupled IA achieves a 53.9 dB signal-to-noise and distortion ratio (SNDR) and 69.5 dB total harmonic distortion (THD).

A Wide-Band Magnetoelectric Sensor Based on a Negative-Feedback Compensated Readout Circuit.

Magnetoelectric (ME) sensors cannot effectively detect broadband magnetic field signals due to their narrow bandwidth, and existing readout circuits are unable to vary the bandwidth of the sensors. To expand the bandwidth, this paper introduces a negative-feedback readout circuit, fabricated by introducing a negative-feedback compensation circuit based on the direct readout circuit of the ME sensor. The negative-feedback compensation circuit contains a current amplifier, a feedback resistor, and a feedback coil. For this purpose, a Metglas/PVDF/Metglas ME sensor was prepared. Experimental measurements show that there is a six-fold difference between the maximum and minimum values of the ME voltage coefficients in the 6-39 kHz frequency band for the ME sensor without the negative-feedback compensation circuit when the sensor operates at the optimal bias magnetic field. However, the ME voltage coefficient in this band remains stable, at 900 V/T, after the charge amplification of the direct-reading circuit and the negative-feedback circuit. In addition, experimental results show that this negative-feedback readout circuit does not increase the equivalent magnetic noise of the sensor, with a noise level of 240 pT/√Hz in the frequency band lower than 25 kHz, 63 pT/√Hz around the resonance frequency of 30 kHz, and 620 pT/√Hz at 39 kHz. This paper proposes a negative-feedback readout circuit based on the direct readout circuit, which greatly increases the bandwidth of ME sensors and promotes the widespread application of ME sensors in the fields of broadband weak magnetic signal detection and DBS electrode positioning.

A high-gain wideband balun-LNA with multiple noise-optimized technique

This article reports a high-gain wideband low-noise amplifier (LNA) with single ended input and differential output for multi-standard wireless receiver operating in 0.2 to 7 GHz. The proposed balun-LNA is cascode structure with common-gate–common-source (CG–CS) balun load to achieve single to differential conversion. Focusing on improving the voltage gain, bandwidth and noise performance at the same time, several techniques are implemented in this balun-LNA. A current source is added shunting CG stage to relieve voltage headroom and improve gain and linearity. Wideband input matching is achieved by active shunt-shunt resistive feedback, together with the input series inductor. Moreover, feedforward and current-reuse technique are introduced to further optimize the noise performance. The proposed LNA has a measured voltage gain of 26 dB which is nearly 6 dB higher than other balun-LNA with same supply and process. Moreover, the minimum noise figure (NF) is 2.0 dB owing to multiple noise-optimized technique. The achieved input power at 1 dB gain compression point (IP1 dB) is −14 dB m at 1 GHz and input return loss (S11) is better than −10 dB across entire operating frequency range. IIP3 and IIP2 achieve −7 dBm and 25 dBm respectively, measured at 1 GHz. The power consumption is 15.5 mW at 1.2 V supply. The LNA is fabricated in 130 nm CMOS process and the active area is 0.097 mm2. The LNA achieves high voltage gain and wide operating frequency range with low NF, which can be reflected from the figure of merit (FOM) of 23.1.

Spectroscopic effects of distributed-line phenomena in integrated feedback resistors for charge-sensitive pre-amplifiers

The distributed capacitive coupling of high-valued resistors with ground planes modifies their effective impedance and power spectral density of noise, especially at high frequency. This effect is clearly visible in poly-silicon resistors inside integrated circuits. When such resistors are used in the feedback network of Charge Sensitive Pre-amplifiers an excess noise arises with a non-white noise spectral density. The effect is a worsening of the spectroscopic resolution. The relevance of such effect with respect to the conventional noise sources is discussed in different practical cases.

Comparison and influence of 1011 and 1013 ohm resistors used for MC-ICP-MS determination of isotope ratios in highly enriched silicon

Use of high ohmic feedback resistors connected with Faraday cups enables strong reduction of sample size (here: Si crystal slices enriched in 28Si) and proper signal quality while maintaining the measurement uncertainty.

Metabolic engineering of Corynebacterium glutamicum for the production of anthranilate from glucose and xylose.

Anthranilate and its derivatives are important basic chemicals for the synthesis of polyurethanes as well as various dyes and food additives. Today, anthranilate is mainly chemically produced from petroleum-derived xylene, but this shikimate pathway intermediate could be also obtained biotechnologically. In this study, Corynebacterium glutamicum was engineered for the microbial production of anthranilate from a carbon source mixture of glucose and xylose. First, a feedback-resistant 3-deoxy-arabinoheptulosonate-7-phosphate synthase from Escherichia coli, catalysing the first step of the shikimate pathway, was functionally introduced into C. glutamicum to enable anthranilate production. Modulation of the translation efficiency of the genes for the shikimate kinase (aroK) and the anthranilate phosphoribosyltransferase (trpD) improved product formation. Deletion of two genes, one for a putative phosphatase (nagD) and one for a quinate/shikimate dehydrogenase (qsuD), abolished by-product formation of glycerol and quinate. However, the introduction of an engineered anthranilate synthase (TrpEG) unresponsive to feedback inhibition by tryptophan had the most pronounced effect on anthranilate production. Component I of this enzyme (TrpE) was engineered using a biosensor-based invivo screening strategy for identifying variants with increased feedback resistance in a semi-rational library of TrpE muteins. The final strain accumulated up to 5.9 g/L (43 mM) anthranilate in a defined CGXII medium from a mixture of glucose and xylose in bioreactor cultivations. We believe that the constructed C. glutamicum variants are not only limited to anthranilate production but could also be suitable for the synthesis of other biotechnologically interesting shikimate pathway intermediates or any other aromatic compound derived thereof.