Resistive Array Research Articles

Resistive RAM arrays with multiple bits

Resistive RAM arrays with multiple bits

Resistive switching device with highly-asymmetric current-voltage characteristics: its error analysis and new design parameter

As a solution to future non-volatile random access memories (NV-RAMs) with large scale integration, many researchers are studying a crossbar array built with many resistive switching cells because of its simple architecture and scalability. However, a sneak current in the crossbar array that energizes memory cells not explicitly selected, raises various issues that need to be addressed for commercialization. Hence, we clearly describe the dominant causes and considerations for a passive crossbar array based on memristors. We discover that such resistive switches under reverse bias along the sneak current paths can play an important role to minimize the overall sneak current by blocking their reverse current. To develop commercializable passive crossbar resistive switching arrays, we demonstrate a read error bound and propose a new design parameter (RRL/RFL as ratio of reverse low resistance state and forward low resistance state) using the switching resistances on the forward and reverse current paths.

Mask Technique for Fast and Efficient Training of Binary Resistive Crossbar Arrays

Resistive crossbar arrays, despite their advantages such as parallel processing, low power, and high density, suffer from the sneak path problem created by IR voltage drops. The crossbar non-idealities considerably degrade the accuracy of matrix multiplication operation, which is the cornerstone of hardware accelerated neural networks. In this paper, we propose a novel technique to capture the sneak path problem to enable off-chip learning and weight transfer. The proposed technique can be easily integrated into any neural network training framework. Performance results show a significant improvement after retraining the network with the proposed mask technique. Two mask solutions have been proposed and studied to capture the sneak path problem in resistive crossbar arrays. Both mask solutions were successfully able to achieve classification accuracy close to the baseline accuracy. The tradeoffs between the two solutions are discussed and compared in terms of accuracy, power, and area.

Data retention investigation in Al:HfO2-based resistive random access memory arrays by using high-temperature accelerated tests

In this work, the feasibility of using accelerated tests at high temperatures to assess the data retention on resistive random access memory devices was evaluated on Al:HfO2-based 1-transistor-1-resistor 4 kbit arrays. By annealing the samples at four different temperatures (190, 210, 230, and 260°C) for 10 h, different distributions of retention failure times were obtained and modeled by using Weibull distributions. Based on the temperature dependency of these distributions, the Arrhenius activation energy of the degradation process was calculated (1.09 eV). In addition, the maximum temperature that guarantees a retention time to failure of a 10 year lifetime was extrapolated (105°C).

An Improved Algorithm for Drift Diffusion Transport and Its Application on Large Scale Parallel Simulation of Resistive Random Access Memory Arrays

A hybrid finite volume–finite element method which can avoid overestimation of volume shared by each vertex in the meshing grid is proposed to solve the diffusive transport governed continuity equation. The simulation results demonstrate that the improved algorithm can eliminate unphysical distortions as compared to the conventional Scharfetter Gummel method. Based on the proposed algorithm, a parallel-computation simulator is developed for large-scale electrothermal simulation of resistive random access memory (RRAM) arrays, in which the domain decomposition method and J parallel adaptive unstructured mesh applications infrastructure are adopted. The validity, speedup, and scalability of the parallel simulator are investigated on the TianHe-2 supercomputer. Based on the simulated results, the electrothermal characteristics and reliability analysis of large-scale RRAM arrays are investigated in detail.

基于回路的MOS电阻阵单像素红外模型建模方法研究

基于回路的MOS电阻阵单像素红外模型建模方法研究

Accelerating <inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula>-Medians Clustering Using a Novel 4T-4R RRAM Cell

Clustering is a crucial tool for analyzing data in virtually every scientific and engineering discipline. The U.S. National Academy of Sciences has recently announced “the seven giants of statistical data analysis” in which data clustering plays a central role. This report also emphasizes that more scalable solutions are required to enable time and space clustering for the future large-scale data analyses. As a result, hardware and software innovations that can significantly improve energy efficiency and performance of the data clustering techniques are necessary to make the future large-scale data analysis practical. This paper proposes a novel mechanism for computing bit-serial medians within resistive RAM arrays with no need to read out the operands from memory cells. We propose a novel four-transistor, four-memristor memory cell that enables in situ median computation within the data arrays. (If necessary, the proposed cell could be used as four ordinary one-transistor, one-memristor memory cells to store four bits of information.) The proposed hardware is used to accelerate a data clustering library using breast cancer samples, indoor localization, and the U.S. Census data sets, as well as two applications using ${k}$ -means clustering. Our simulation results for the library indicate an average performance improvement of $15.5\times $ and an energy reduction of $28.5\times $ over a baseline CPU system. Also, we observe an overall speedup of $5.8\times $ with an energy improvement of $14.1\times $ over a baseline processing-in-memory accelerator. For the ${k}$ -means applications, we observe speedups of $45.7\times $ and $1.5\times $ with respective energy improvements of $49.5\times $ and $1.3\times $ as compared with the CPU baseline.

Neuroinspired unsupervised learning and pruning with subquantum CBRAM arrays

Resistive RAM crossbar arrays offer an attractive solution to minimize off-chip data transfer and parallelize on-chip computations for neural networks. Here, we report a hardware/software co-design approach based on low energy subquantum conductive bridging RAM (CBRAM®) devices and a network pruning technique to reduce network level energy consumption. First, we demonstrate low energy subquantum CBRAM devices exhibiting gradual switching characteristics important for implementing weight updates in hardware during unsupervised learning. Then we develop a network pruning algorithm that can be employed during training, different from previous network pruning approaches applied for inference only. Using a 512 kbit subquantum CBRAM array, we experimentally demonstrate high recognition accuracy on the MNIST dataset for digital implementation of unsupervised learning. Our hardware/software co-design approach can pave the way towards resistive memory based neuro-inspired systems that can autonomously learn and process information in power-limited settings.

Circuit arrangement to suppress crosstalk in chemo‐resistive sensor arrays

Modern electronic nose and such systems, typically employ gas sensors in arrays. Access to the individual elements in an m × n resistive sensor array requires m + n interconnect lines and effect of crosstalk becomes inevitable. The crosstalk is caused due to the leakage currents in the multiplexer channels as well as the parasitic paths among the non-selected elements in the array. Here, the authors present a novel circuit arrangement to suppress crosstalk in two-dimensional chemo-resistive sensor arrays. The proposed circuit employs a transistorised bypassing scheme, diodes in series and voltage feedback to non-selected elements of an array for crosstalk elimination. Simulation results of a resistive sensor array are presented. Finally, the proposed arrangement has been applied on an 8 × 2 sensor array and the result has been compared with the same array with a normal feedback arrangement for data acquisition. The work can also be extended for general resistive sensor arrays.

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design

This paper presents a design of strong physical unclonable function (PUF) exploiting the sneak paths in the resistive X-point array. The entanglement of the sneak paths in the X-point array greatly enhances the entropy of the physical system, thereby increasing the space of challenge-response pairs. To eliminate the undesired collision or diffuseness in X-point PUF with “analog” resistance distribution and “digital” resistance distribution is employed in this paper. The effect of design parameters and non-ideal properties in X-point array on the performance of X-point PUF is systematically investigated by Simulation Program with Integrated Circuit Emphasis (SPICE) simulation. The simulation results show that—1) the PUF’s performance presents strong dependence on the percent of cells in the on-state, thus should be carefully optimized for the robustness against the reference current variation of the sense amplifier; 2) the interconnect resistance decreases the column current thus the reference current should scale down with the scaling of technology node; 3) larger on/off ratio is desired to achieve low power consumption and high robustness against reference current variation; and 4) the device-to-device variation might degrade the performance of X-point PUF, which can be mitigated with write-verify programming scheme in the PUF construction phase. In addition, the proposed X-point PUF presents no correlation between challenges and responses, and strong security against the possible SPICE modeling attack and machine learning attack. Compared with the conventional Arbiter PUF, the X-point PUF has benefits in smaller area, lower energy, and enhanced security.

Unveiling the Switching Mechanism of a TaO<italic>x</italic>/HfO2 Self-Selective Cell by Probing the Trap Profiles With RTN Measurements

Self-selectivecells (SSCs) with built-in nonlinearity provide a promising solution for overcoming the leakage current issue of 3-D vertical resistive random access memory arrays. However, deep understanding of the switching mechanism of the SSC device is still lacking, hindering the effective improvement of the device performance. In this letter, we investigated the switching mechanism of the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SSC device by probing the trap profiles with RTN measurements. Both the vertical locations and energy levels (X <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of defects in the HRS and LRS could be calculated by the bias-dependence of the capture and emission time constants (τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> and τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ). Using the comparison of the defect profiles before and after the resistive switching, an active region in the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> layer adjacent to the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer could be clearly identified. Based on these results, a clear picture of resistive switching in the TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SSC was obtained.

Oxide TFT Comparator Suitable for Bio Sensor Platform

As the interest in personal health care is increasing, research on Bio-Information Technology (BIT) continues to be as vigorous as ever. Particularly, efforts are being made to develop products using bio-sensors capable of free movement and prompt detection. Therefore, a health care device with SOG (System-on-glass) technology is required due to the advantages of miniaturization, low cost, and simple process. These bio-sensor platforms must be consisting of the fully integrated circuit in order to be in contact with or embedded in the human body. To display the sensing signal, we need analog-to-digital converter (ADC) circuit and 7-segment decoder which can be integrated using n-type amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on a substrate. These bio-sensor platforms consist of an integrated circuit that converts the analog signal to a digital signal and the 7-segment decoder to show the signal level. TFTs are required to realize the SOG which integrates all devices on substrates like a glass and plastic etc. Oxide semiconductor TFTs such as a-IGZO TFTs show better performance than amorphous silicon TFTs. Owing to their transparency and higher mobility compared to the amorphous silicon TFTs, a-IGZO TFTs have been studied widely. Figure shows 9 comparators for digitizing, 9-to-4bit priority encoder and 7-sement decoder for display. An OP amp-based comparator includes two inputs, one is an analog input (Vin) and the other is a reference voltage (Vref) generated by a serially connected resistor array. The input signals are compared with the reference voltages by the comparators, which output “0” or “1” according to the analog input level. Then the binary outputs of the comparator are converted to the binary format (A3, A2, A1, and A0) by a digital encoder. The 4bit outputs (A3, A2, A1, and A0) of the ADC are the inputs of the 7-segment decoder. Among the four outputs of ADC, ‘A0’ is the least significant bit and ‘A3’ is the most significant bit. The outputs of 7-segment decoder are labelled as a, b, c, d, e, f, and g which correspond to each segment of 7-segment display. The 4bit binary codes from ADC are converted to input signals (a to g) of a 7-segment display. Those circuits with a-IGZO TFTs can be used in applications such as the fully integrated bio-sensor platform and wearable device which are transparent and flexible. The most complex one in that platform is OP Amp which is comparator to generate binary code and needs high gain to accomplish good performance. The comparator is a circuit that plays an important role in the ADC, and the operation of the ADC is difficult to expect without the correct operation of the operational amplifier. Thus, we proposed OP Amp type comparator with oxide TFT for bio sensor platform. Figure 1

Improving Accuracy in the Readout of Resistive Sensor Arrays

The most efficient way to carry out the reading of a set of resistive sensors is to organize them in an array form. This reduces the number of wires to the sum of the number of rows, M, and columns, N, and reading can be carried out using just M+N multiplexers and a single operational amplifier. The drawback in this procedure is the appearance of crosstalk (the influence of the resistance of some sensors on the measurements of others). Although different proposals have been presented in the literature to reduce this phenomenon, errors in determining the resistance values of each sensor still exist in all the proposals. This article presents a new method to determine these values, which considerably reduces errors without the need for any hardware other than the simplest reading circuits. The method consists of a very fast recursive convergence procedure. The results show that the new proposal outperforms other solutions in the first or second step.

Improved resistance matrix approach for readout of the two-dimensional resistive sensor array

In the readout circuits of the two-dimensional (2-D) resistive sensor arrays, various auxiliary electrical components were used to reduce their crosstalk errors but resulted in increased circuit complexity. Readout circuits with low-complexity structures were necessary for wearable electronic applications. With only several resistors and a microcontroller, readout circuit based on resistance matrix approach (RMA) achieved low complexity but suffered from small resistance range and large measurement error caused by the output ports’ internal resistances of the microcontroller. For suppressing those negative effects, we firstly proposed an improved resistance matrix approach (IRMA) by additionally sampling the voltages on all driving row electrodes in the RMA. Then the effects of the output ports’ internal resistances and the analog-to-digital converter’s accuracy for the RMA and the IRMA were simulated respectively with NI Multisim 12. Moreover, a prototype readout circuit based on the IRMA was designed and tested in actual experiments. The experimental results demonstrated that the IRMA, though it required more sampling channels and more computations, could be used in those applications needing low complexity, small measurement error and wide resistance range.

An On-Chip Trainable and the Clock-Less Spiking Neural Network With 1R Memristive Synapses.

Spiking neural networks (SNNs) are being explored in an attempt to mimic brain's capability to learn and recognize at low power. Crossbar architecture with highly scalable resistive RAM or RRAM array serving as synaptic weights and neuronal drivers in the periphery is an attractive option for the SNN. Recognition (akin to "reading" the synaptic weight) requires small amplitude bias applied across the RRAM to minimize conductance change. Learning (akin to "writing" or updating the synaptic weight) requires large amplitude bias pulses to produce a conductance change. The contradictory bias amplitude requirement to perform reading and writing simultaneously and asynchronously, akin to biology, is a major challenge. Solutions suggested in the literature rely on time-division-multiplexing of read and write operations based on clocks, or approximations ignoring the reading when coincidental with writing. In this paper, we overcome this challenge and present a clock-less approach wherein reading and writing are performed in different frequency domains. This enables learning and recognition simultaneously on an SNN. We validate our scheme in SPICE circuit simulator by translating a two-layered feed-forward Iris classifying SNN to demonstrate software-equivalent performance. The system performance is not adversely affected by a voltage dependence of conductance in realistic RRAMs, despite departing from linearity. Overall, our approach enables direct implementation of biological SNN algorithms in hardware.

P‐136: Resistive Type 2D Mapping Positional Strain Sensor Array for Advanced Tactile Displays

In this research, a new strain sensor array for measuring positional strain distribution have been demonstrated by using silver nanowire coated poly‐urethane fiber and composite blended with carbon black and PDMS, as insensitive and sensitive elements, respectively. Unit strain sensor with both insensitive and sensitive elements can be stretched up to 50 % and has a good sensitivity (Gauge factor; G.F ≈ 6), which is enough to detect human skin's movement. For positional strain distribution under external stimuli, we fabricated large area strain sensor arrays with 10 x 10 pixel and high resolution. Furthermore, to verify the measurement condition and obtained data of sensor array, we performed fine element analysis (FEA) simulation. This simulation result indicated that the fabricated strain sensor array can detect the relative strain values and their strain distribution when a strain was applied to this sensor array.

Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics

Artificial Neural Network computation relies on intensive vector-matrix multiplications. Recently, the emerging nonvolatile memory (NVM) crossbar array showed a feasibility of implementing such operations with high energy efficiency. Thus, there have been many works on efficiently utilizing emerging NVM crossbar arrays as analog vector-matrix multipliers. However, nonlinear I-V characteristics of NVM restrain critical design parameters, such as the read voltage and weight range, resulting in substantial accuracy loss. In this article, instead of optimizing hardware parameters to a given neural network, we propose a methodology of reconstructing the neural network itself to be optimized to resistive memory crossbar arrays. To verify the validity of the proposed method, we simulated various neural networks with MNIST and CIFAR-10 dataset using two different Resistive Random Access Memory models. Simulation results show that our proposed neural network produces inference accuracies significantly higher than conventional neural network when the network is mapped to synapse devices with nonlinear I-V characteristics.

Experimental Investigation of Measurement Error in Networked Resistors Arrays Based on Zero Potential Method

This paper provides a comprehensive study on the zero potential method for restriction of the crosstalk-based measurement error in network resistor arrays. We introduce four circuits with different architectures based on the zero potential method to comparatively study the effect of the switches on-resistance on the measurement error. Moreover, the effect of the operational amplifiers with different specifications on the measurement error will be investigated. The results show that the measurement error introduced by the onresistance of the switches can be effectively suppressed by inserting a buffer between the sensing elements and the switches on each driven electrode, and utilizing the virtual ground of the trans-impedance amplifier on each scanned electrode. We will show that, the efficiency of the circuits on elimination of the measurement error may be improved by employing high precision operational amplifiers.

Operational characteristics of the superconducting high flux plasma generator Magnum-PSI

The interaction of intense plasma impacting on the wall of a fusion reactor is an area of high and increasing importance in the development of electricity production from nuclear fusion. In the Magnum-PSI linear device, an axial magnetic field confines a high density, low temperature plasma produced by a wall stabilized DC cascaded arc into an intense magnetized plasma beam directed onto a target. The experiment has shown its capability to reach conditions that enable fundamental studies of plasma-surface interactions in the regime relevant for fusion reactors such as ITER: 1023–1025 m−2s−1 hydrogen plasma flux densities at 1–5 eV for tens of seconds by using conventional electromagnets. Recently the machine was upgraded with a superconducting magnet, enabling steady-state magnetic fields up to 2.5 T, expanding the operational space to high fluence capabilities for the first time. Also the diagnostic suite has been expanded by a new 4-channel resistive bolometer array and ion beam analysis techniques for surface analysis after plasma exposure of the target. A novel collective Thomson scattering system has been developed and will be implemented on Magnum-PSI. In this contribution, the current status, capabilities and performance of Magnum-PSI are presented.

Improved FRZPC for the two‐dimensional resistive sensor array

With M sampling operational amplifiers (op-amps) in negative feedback, the fast readout zero potential circuit (FRZPC) can simultaneously access M elements in the M × N resistive sensor array with the shared row–column fashion but it suffered from the crosstalk problem caused by the switch-on resistance of the column multiplexers, the non-scanned elements and the size of the array. For suppressing the crosstalk problem, the authors proposed an improved FRZPC, called IFRZPC, by introducing one more op-amp in negative feedback to sample the current in the ground to the array direction. Then, in the FRZPC and the IFRZPC, the effects of different parameters of the resistive sensor array and the readout circuit on the measurement accuracy of the elements being tested were simulated using National Instrument Multisim. Simulations and comparative experiments were performed and demonstrated that IFRZPC, though requiring M + 1 op-amps, M + 1 resistors, and M + 1 sampling channels, could simultaneously access M elements being tested on the same column in the M × N resistive sensor array with a better accuracy.