Resistance RDS Research Articles

Investigation of the Trapping and Detrapping Behavior by the On-State Resistance at Low Off-State Drain Bias in Schottky p-GaN Gate HEMTs

GaN power HEMTs enable the design of power electronic systems with highest efficiencies and reduced size. Despite strong advancements in device reliability, charge carrier trapping is still an important challenge. The applied methodology allows to characterize defects that cause the dynamic RDS,on in GaN power devices at product level with flexibility in duty cycle, number of pulses and mission profile. A pronounced trapping is observed for lateral GaN-on-Si HEMTs with Schottky p-GaN gate structure at low drain bias and long off-state pulses (> 100 ms). The effect is investigated by fast determination of the on-state resistance RDS,on under different trap capturing conditions: a) different drain bias b) off-state time and number of cycles c) variation of temperature. The trapping and detrapping effects are characterized and the activation energy is extracted from time constants. An elevated on-state resistance was present for up to 3 hours. The threshold voltage modification due to high drain bias does explain the significant RDS,on increase.

Online die temperature measurement using S-parameters in GaN-based power converters

Die temperature (Tj) measurement of GaN HEMTs is of high interest to enable reducing design margin and the implementation of reliability driven control schemes and protections. On-state resistance (Rds,on) has been identified as a relevant thermo-electric sensitive parameter (TSEP) for Tj measurement requiring no extra temperature sensor. It is commonly measured in time-domain, based on the on-state voltage drop and the load current. In this work, the Tj of a GaN-on-Si power IC in a dc-dc converter is deduced from measurements conducted online, directly in the frequency domain using RF injection and S-parameter measurements. Thereby, the stimulus is injected on top of the processed power to probe either Rds,on, or the resistance of an on-chip Schottky diode used as thermal sensor. Temperature dependent experimental validation up to 150 °C is performed on a switching dc-dc power converter, validating the approach for online temperature measurement using RF injection.

Optimized recess etching criteria for T‐gate fabrication achieving ft = 290 GHz at Lg = 124 nm in metamorphic high electron mobility transistor with In0.7Ga0.3As channel

AbstractThe authors propose criteria for recess etching to fabricate T‐gate used in InGaAs high electron mobility transistors (HEMTs). By patterning additional rectangular pads on the source and drain metals in the e‐beam lithography step, it is possible to measure the drain‐to‐source resistance (Rds) and current (Ids). The ratio (Γ) of before and after etching for each Rds and Ids can be used as criteria to determine the point in time to stop etching. By performing recess etching with Γ= 1.97 for Rds and Γ= 0.38 for Ids on an epiwafer having cap doping concentration of 2 × 1019 cm−3 and channel indium content of 0.7, the authors have fabricated InGaAs metamorphic high electron mobility transistor (mHEMT) device showing gm,max= 1603 mS/mm and ft= 290 GHz at Lg= 124 nm. The criteria presented can be applied to InGaAs HEMTs with various epitaxial structures.

Ultra high step‐up soft‐switching DC/DC converter using coupled inductor and interleaved technique

AbstractIn this paper, a new ultra high step‐up soft‐switching DC/DC converter using coupled inductor and interleaved technique is presented. The primary side of the coupled inductors in up section and down section will be charged by the input power supply. The stored energy of the coupled inductors (at primary and secondary sides) is discharged to the output capacitors in up and down sections. Also, the capacitors on the coupled inductors path have clamped capacitors that cause the voltage stress across the power semiconductors to be low. Al diodes in up and down sections except output diodes are working at zero current switching turn‐off. Therefore, the reverse recovery problems of the proposed converter will be majorly solved. Therefore, power losses of the proposed converter will be decreased by using switches with lower on‐state resistance RDS(on) and lower rating power diodes. In addition, the leakage inductor causes to exclusive the current falling balance of the output diodes, significantly. In order to clarify the main advantages of the proposed converter, comparison between the proposed converter and other structures is provided. Finally, the proposed converter with turn ratio N(N2/N1) = 2 in about 300 W with operating 50 kHz is tested with real‐time TYPHOON HIL‐404 emulator in the laboratory.

A Comprehensive loss analysis of SiC-based DAB DC-DC converter for electric vehicle application

This paper presents loss analysis of SiC MOSFET based bidirectional DAB (Dual Active Bridge) DC-DC converter for EV application. This converter benefits the efficiency of the EV vehicle by reducing power loss and voltage drop across the converter. The DAB uses WBG (Wide-Bandgap) semiconductor devices such as SiC MOSFET to optimize the efficiency and extend soft-switching over whole operating range. The SiC MOSFET switching devices rated at 1200 V with different drain- source on-state resistance Rds(on) of 21 mΩ/32 mΩ is considered. Therefore, a reliable converter rated at 10 kW which works under normal operating condition at high-switching frequency of 100 kHz. The switching and conduction losses are taken under two different junction temperature such as 25 °C and 100 °C with various operating load current between 10 A to 40 A. Based on an analysis of SiC MOSFET based DAB attains 98.8% efficiency. The simulation results are taken as voltage and current waveforms at various points of converter are reported. This SiC based DAB converter would be used in next generation of V2G (Vehicle-to-Grid) and G2V (Grid-to-Vehicle) technology.

Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

This paper focuses on the enhancement of the robustness level of SiC MOSFET during short-circuit conditions. In this study, two approaches allowing to ensure safe “Fail-To-Open” (FTO) mode in planar power SiC MOSFET devices under short-circuit operation are presented. These approaches are based on direct depolarization of the gate source voltage and its estimation from the calculation of the critical dissipated power (W/mm2) between FTO and classical unsafe thermal runaway. They allow to determine the maximum value of the gate source voltage to preserve a FTO mode under a drain source voltage close to the nominal value i.e. VBRmin/2. The boundary of the power density between FTO and “Fail-To-Short” (FTS) is introduced. A complete experimentation of the two failure modes in competition that may appear during short-circuit (SC) test of 1.2 kV SiC MOSFETs is presented. Finally, the penalty of the gate source voltage depolarization on the on-state resistance (Rds(on)) is investigated in order to evaluate the techniques efficiency.

No-Isolated High Gain DC/DC Converter with Low Input Current Ripple Suitable for Renewable Applications

In this paper, a new non-isolated high voltage gain dc/dc converter with low input current ripple is proposed for renewable sources applications. The proposed converter combined SEPIC converter and voltage multiplier cells. In order to achieve high voltage gain, the proposed converter can increase the output voltage level using the voltage multiplier unit. The voltage stress across the semiconductors will be decreased compared to SEPIC, conventional boost converter. Therefore, using only one switch with lower resistance RDS(on), the overall efficiency of the proposed converter is increased significanly. In order to verify the theoretical analysis of the proposed converter and its accurate operation, a 150 W prototype operating at 25 kHz is built and tested.

High step-up interleaved dc/dc converter with high efficiency

ABSTRACT In this paper, a new non-isolated Interleaved dc/dc converter with high-voltage conversion ratio is presented. The proposed converter combined with interleaved converter techniques and voltage multiplier cell (diode/capacitor/inductor). The voltage stress across the power semiconductors (power MOSFETs/diodes) is decreased compared to SEPIC, conventional boost converter. The low normalized stress causes to using the low rating semiconductors. In fact, the overall efficiency of the proposed converter will be increased by using MOSFETs with lower resistance R DS(on) and lower ranges for power diodes. To confirm the accuracy theoretical analysis of the proposed converter and operation converter, a laboratory prototype in about 190 W with operating at 40 kHz is built and tested.

Prognostics of Power MOSFET Using Artificial Neural Network Approach

This paper presents the prognostics of in-circuit power MOSFETs in power electronic systems using artificial neural network (ANN). Recent industrial surveys on reliability of power electronic systems shows that the switching transistors are one of most life-limiting component and thermal stress is major cause for their parametric degradation. The on-state drain-source resistance (Rds(on)) is an important fault signature parameter of power MOSFET which increases with its junction temperature rise. In this work, ANN is used to estimate variation in Rds(on) of target MOSFETs at different operating conditions. The data set for training and testing of proposed back-propagation trained artificial neural network are experimentally obtained from the developed test bed. Using test bed, the electrical stressed based accelerated aging test is performed on target power MOSFETs by subjecting them to repetitive unclamped inductive switching at different operating frequency and temperature. After off-line training, the proposed ANN is implemented using National Instruments LabVIEW software to estimate real-time Rds(on) values of in-circuit MOSFETs. For this purpose, voltage fed half bridge inverter circuit is designed and target MOSFETs are taken at output section of the circuit. A low cost microcontroller is programmed for acquiring and serially transmitting the real-time data set of target MOSFETs to the LabVIEW software. The performance of the proposed method is evaluated in real time by comparing the ANN estimated Rds(on) value with the experimental obtained value for in-circuit target MOSFETs at test condition.

Investigation of the aging of power GaN HEMT under operational switching conditions, impact on the power converters efficiency

This paper investigates the aging of a 650 V, 30 A GaN HEMT power transistor under operational switching conditions. The switching stress respects the Safe Operation Area (SOA) of the tested transistor. The aging campaign lasted 1008 h and was carried out through a developed switching application with high power efficiency. The global aging results show the degradation of five parameters: drain current ID, on-state resistance RDS(ON), transconductance gm, gate leakage current IGSS, and threshold voltage VTH. The major causes that affect the reliability of the GaN HEMT are hard switching, long time of test and high intensity of the stress. The existence of trapped charge in the gate-drain access region after aging is demonstrated using pulsed measurements. The effects of this degradation on power converters are studied by modeling the static characteristics of the aged GaN HEMT using an accurate method based on the Levenberg-Marquardt Algorithm. The accuracy and consistent convergence of the developed SPICE model provide a good way to investigate the reliability of GaN HEMTs by a simulation approach.

A multi‐input‐single‐output high step‐up DC‐DC converter with low‐voltage stress across semiconductors

In this paper, a new extendable high step-up multi-input-single-output dc-dc converter is presented. The proposed converter is composed based on the conventional boost converter and conventional buck-boost converter. The benefits of the proposed converter consist of the simple control of each duty cycle and low-voltage stress across the semiconductors. Therefore, conduction losses can be reduced by using the switch with lower resistance rDS(on). The presented converter is flexible to obtain the high power level with the proper selection of duty cycle values. Therefore, the presented converter is controllable in different power levels of input sides. In fact, the proposed converter supports the operation of multiple input sources without any changes in the structure of the topology. The dynamic modeling and efficient multivariable controller design with dynamic responses for the proposed converter are analyzed completely. To confirm the performance of the presented converter, mathematical analysis and simulation results are presented. In addition, the comparison between the presented converter and some other topologies is provided. In order to illustrate the efficient operation of the presented converter, a laboratory prototype for a 425 V/300 W with 40- and 45-V input voltages and 95.62% efficiency is implemented.

Analysis, modeling, and implementation of a new transformerless semi‐quadratic Buck–boost DC/DC converter

SummaryThis paper presents a novel transformerless semi‐quadratic buck‐boost converter (SQBuBoC). In the proposed SQBuBoC, two power switches with simultaneous operation are used and a higher step‐up/step‐down voltage conversion ratio is achieved compared with the traditional buck‐boost, Cuk, single‐ended primary‐inductor converter, and Zeta converters. The positive polarity of the output voltage, along with low ripple continuous input current and common ground between the source and the output voltages, are some features that make the suggested topology more suitable for many applications with wide range of output voltage such as photovoltaic systems. Moreover, the total voltage stress across the power switches in this converter is lower than the cascade boost, and the traditional buck‐boost converters led to power MOSFETs selection with lower drain‐source ON resistance (Rds) and efficiency improvement. All the steady‐state analysis and comparisons in continuous conduction mode (CCM) are discussed in details. In addition, to study the low frequency behavior of the SQBuBoC by means of the state‐space averaging technique, the small and large signal models of this converter in CCM are presented. Finally, the SQBuBoC analysis is justified using experimental results of a 50 W step‐up 25 V to 120 V and a 28 W step‐down 25 V to 14 V laboratory prototypes.

High step‐up DC–DC converter using one switch and lower losses for photovoltaic applications

In this study, a new non-isolated high step-up dc-dc converter using one switch and low-voltage stress on semiconductors is presented for photovoltaic applications. The proposed converter consists of one switch in the input side ( S ), voltage multiplier units (D-C-L), one diode in the output side ( D o ) and one capacitor ( C o ). To achieve high-voltage gain and power level, the proposed converter can be extended to n stages of voltage multiplier units. Hence, the output voltage level will be reasonably increased and the nominal value of power devices will be decreased. Therefore, the voltage stress across the power switch is decreasing for different duty cycles at high power levels. As a result, the efficiency of the proposed converter can be increased by using one switch with lower resistance r DS(on) . To verify the carried mathematical analysis of the proposed converter and circuit implementation are validated through both the simulation and experimental results that accordance each other well. The experimental results of two prototypes (with n = 2, 3) in about 290 W operating at 33 kHz are provided.

On-State Voltage Measurement of Fast Switching Power Semiconductors

The on-state resistance R ds,on is a key characteristic of unipolar power semiconductors and its value depends on the operating conditions, e.g. junction temperature, conducted current and applied gate voltage. Hence, the exact determination of the R ds,on value cannot rely on datasheet information and requires the measurement of current and on-state voltage during operation. Besides the determination of the conduction losses, the on-state voltage measurement enables dynamic R ds,on analysis, device temperature estimation, condition monitoring and consequently time-to-failure prediction. However, in contrast to a switch current measurement, several challenges arise in the design of an on-state voltage measurement circuit (OVMC), i.e. high measurement accuracy (mV-range) during on-state, high blocking voltage capability (kV-range) during off-state and fast dynamic response (ns-range) during switching transitions are demanded. Different OVMC concepts are known from IGBT applications, however, the more severe requirements introduced from the high switching frequency and low OV characterizing the operation of fast switching power semiconductors, prevent their usage. Off-the-shelf products hardly satisfy the mentioned specifications, whereas the performance of state-of-the-art OVM research prototypes require further investigations and/or improvements. With this aim, an innovative OVMC concept is designed, analyzed, calibrated and tested in this paper. Furthermore, the conduction losses of different power semiconductors are measured as function of their operating conditions to validate the performance and highlight the potential of the proposed OVMC.

A novel high step-up DC–DC converter based on three-winding coupled inductor

In this paper, a novel boost DC/DC converter is proposed. The existence of the three-winding coupled inductor in the proposed topology causes an increase in voltage gain. Another advantage of suggested topology is that by reducing the turn’s ratio of the coupled inductor the voltage gain of converter is increased. In the proposed converter the stored energy in the leakage inductance is recovered by utilizing a passive clamp circuit. Moreover, in the proposed topology, voltage stress on the main switch is decreased. As a result, a power switch with lower resistance RDS (ON) and the lower number of windings turn are caused to reduction of power losses. Operation rules and steady-state analysis of the proposed converter are explained completely. In order to evaluate the effectiveness of the proposed converter, a 200 W laboratory prototype is implemented. Experimental results approve the theoretical analysis of the proposed high step-up converter.

Analysis of MOCVD SiNx Passivated N-Polar GaN MIS-HEMTs on Sapphire With High $f_{max}\cdot V_{DS,Q}$

This letter presents an analysis of N-polar metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with a 40 nm MOCVD SiNx passivation and a trench-gate design. A device with a 50 nm gate-length ( L g ) demonstrates a 313 GHz power gain cutoff frequency ( f max ) at a quiescent drain bias ( V $_{{DS,Q}}$ ) of 26 V. The high $f_{max}\cdot V_{DS,Q}$ of 8.1 THz $\cdot$ V exhibits great potential of the device in high-frequency power applications. Investigation on small-signal parameters shows that f max improves with V $_{{DS,Q}}$ due to a reduction of gate-drain capacitance ( c gd ) and an increase of output resistance ( rds ). When comparing with the previously reported planar HEMT design, the shorter L g enabled by the trench-gate design enhances the intrinsic current gain cutoff frequency ( f $_{{T,int}}$ ) leading to a higher peak f max at a higher V $_{{DS,Q}}$ .

High conversion ratio DC-DC converter with isolated transformer and switched-clamp capacitor for Taiwan photon source

A new high step-up voltage converter that combines a switch capacitor and isolated transformer, together with a passive clamp circuit, is employed to reduce voltage stress on the main power switch. The voltage stress of the power switch should be clamped to 1/4 Vo, and the proposed converter can achieve high step-up voltage gain with appropriate duty ratio. The energy of the leakage inductor can be recycled by the clamp capacitor because of the passive clamp circuit, and low On-state resistance RDS(on) of the power switch can be adopted to reduce the conduction loss. In this paper, several mathematical derivations are presented, CCM and DCM operating principle are discussed, and experimental results are provided to verify the effectiveness of converter topology. Finally, a 24-V-input voltage to 200-V-output voltage and a 150 W output power prototype converter are fabricated in the laboratory.

Trench-MOSFETs on 4H-SiC

This paper introduces n-channel normally-off Trench-MOSFETs on 4H-SiC featuring a blocking voltage of 600 V and 1200 V. The Trench-MOSFETs exhibit a specific room temperature on-state resistance RDS,on of 1.5 mΩ cm² and 2.7 mΩ cm², respectively. It is shown that a further reduction of the RDS,on by approximately 25 % can be achieved using square-shaped or hexagonal unit cells instead of stripe-shaped unit cells. The Trench-MOSFET switching characteristics using a double pulse setup with a switching current Isw of 100 A and a switching voltage Vsw of 450 V is presented and discussed. The short turn-off and turn-on times in the range of several ten nanoseconds yield large maximum disw/dt and dvsw/dt values, which enable highly efficient power conversion with low switching losses.

Improved modeling on the RF behavior of InAs/AlSb HEMTs

The leakage current and the impact ionization effect causes a drawback for the performance of InAs/AlSb HEMTs due to the InAs channel with a very narrow band gap of 0.35eV. In this paper, the conventional HEMT small-signal model was enhanced to characterize the RF behavior for InAs/AlSb HEMTs. The additional gate leakage current induced by the impact ionization was modeled by adding two resistances RGh1 and RGh2 shunting the Cgs–Ri and Cgd–Rj branches, respectively, and the ionized-drain current was characterized by an additional resistance Rmi parallel with the output resistance Rds, meanwhile the influence of the impact ionization on the transconductance was modeled by an additional current source gmi controlled by Vgs. The additional inductance, evaluated as a function of f(ω,R), was introduced to characterize the frequency dependency of impact ionization by using the impact ionization effective rate 1/τi and a new frequency response rate factor n, which guaranteed the enhanced model reliable for a wide frequency range. As a result, the enhanced model achieved good agreement with the measurements of the S-parameters and Y-parameters for a wide frequency range, moreover, the simulated results of the stability factor K, the cutoff frequency fT, the maximum frequency of oscillation fmax, and the unilateral Mason’s gain U were estimated to approach the experimental results with a high degree.

English

In this paper, to achieve high step-up voltage gain and high efficiency, a novel high step-up ratio using clamp-circuit in addition capacitor and diode along with the boost inductor is proposed. The capacitor gets charged during the switch-off period and discharged during the switch-on period by the energy stored in the inductor which leads to high voltage gain. The leakage-inductor energy of the coupled inductor is recycled with a passive clamp circuit. Thus, the voltage stress on the main switch is reduced. The switch with low resistance RDS is used to reduce the conduction loss which increases the efficiency. The operating principle and steady-state analyses are discussed in detail. Finally, a prototype circuit with 24-V input voltage, 48-V output voltage, is implemented in the laboratory to verify the performance of the proposed converter.