Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

Abstract

This paper focuses on the enhancement of the robustness level of SiC MOSFET during short-circuit conditions. In this study, two approaches allowing to ensure safe “Fail-To-Open” (FTO) mode in planar power SiC MOSFET devices under short-circuit operation are presented. These approaches are based on direct depolarization of the gate source voltage and its estimation from the calculation of the critical dissipated power (W/mm2) between FTO and classical unsafe thermal runaway. They allow to determine the maximum value of the gate source voltage to preserve a FTO mode under a drain source voltage close to the nominal value i.e. VBRmin/2. The boundary of the power density between FTO and “Fail-To-Short” (FTS) is introduced. A complete experimentation of the two failure modes in competition that may appear during short-circuit (SC) test of 1.2 kV SiC MOSFETs is presented. Finally, the penalty of the gate source voltage depolarization on the on-state resistance (Rds(on)) is investigated in order to evaluate the techniques efficiency.