Resistance Of MOSFET Research Articles

Cost-Effective and Scalable Approach to EV Battery Management: MOSFET-Based Passive Cell Balancing

Cell balancing is crucial for preserving battery life and protecting battery cells in order to guarantee the safe and dependable functioning of LiFePo4 batteries on electric vehicles. Because passive cell balancing is inexpensive and simple to perform, BMS routinely uses it. In the passive cell balancing procedure, resistors are used as the balancing element to eliminate excess charge in the battery. Although resistors are inefficient when used with little cells, they are necessary when using large capacity batteries. The internal resistance of MOSFETs, which is utilized as a balancing element, allows for efficient cell balancing. The need for extra balancing components is eliminated by utilizing the MOSFET's intrinsic resistance. The current through the resistance is decreased hence the power losses are minimized and the heat dissipation is also reduced thus, the battery pack temperature is also maintained in the nominal value which decreases the danger of battery damage due to temperature.

Actual Reasons Involving Turn-Off Losses Improvement With Increasing Load and Gate Resistance in MOSFETs Enhanced With Kelvin Source

This paper explains the actual reasons behind the improvement in terms of turn-off energy losses (Eoff) reduction, obtained using Kelvin pin (4-lead, 4L) MOSFETs instead of 3L ones. Eoff increases by increasing gate resistance and load, but the experimental results reveal that the increment is less in 4L than in 3L MOSFETs. Analysing the turn-off waveforms and adopting circuit analysis, the paper first proves that the common argument about the undesired effect of the parasitic source inductance in 3L MOSFETs is misleading. Then, the reasons behind the aforesaid improvement in 4L MOSFETs with increasing gate resistance and load are described by means of the derived analytical expressions. Finally, the analysis of the equations has provided helpful information at the design stage, also accounting for the different device technologies. In particular, the improvement obtained using 4L MOSFETs reduces as the driving loop parasitic inductance increases and evanesces if its value becomes comparable with the power loop parasitic inductance.

Measurement of Very Small Variation of Effective Resistance of MOSFET Deputed in Active Microgrid Inverter Operation

Measurement of Very Small Variation of Effective Resistance of MOSFET Deputed in Active Microgrid Inverter Operation

Extraction of Mobility Degradation and Source-and-Drain Resistance in MOSFETs

A MOSFET model parameters extraction procedure that overcomes the difficulties of separating the effects of source-and-drain series resistance and mobility degradation factor is presented. Instead of the conventional direct fitting, the present procedure involves the use of indirect bidimensional fitting of the source-to-drain resistance of a single device, as obtained from the below-saturation output characteristics measured at several above-threshold gate voltages. The procedure is verified with a simulated long channel FinFET device with externally added resistances and is later applied to experimental planar bulk DRAM MOSFET devices with channel lengths ranging from 0.23μm to 2.0μm. The procedure is shown to be advantageous in terms of computational efficiency and it is appropriate even with high values of externally added series resistances. For the case of devices with various channel lengths, the accuracy of the procedure is improved if the value of RSD is extracted from the shortest channel length. This value of RSD could be used for extracting the other parameters for devices with longer channel.

On the DC extraction of the asymmetric parasitic source and drain resistances for MOSFETs

Two different parameter extraction methods are proposed in this article. First, a simple DC method is presented to extract the difference between the drain and source series resistance of MOSFETs. This method is valid for any three- or four-terminal MOSFET and it can be used in linear, triode or saturation region. Second, an integration-based method is proposed to extract the drain resistance and the source resistance of thin-film MOSFETs. Both methods were tested using simulated and measured data of two different devices: zinc oxide (ZnO) and polysilicon TFTs.

Prognosis of power MOSFET resistance degradation trend using artificial neural network approach

An accurate lifetime prediction of power MOSFET devices is vital for critical applications such as hybrid electric vehicles, high-speed trains and aircrafts. These devices are subject to thermal, electrical and mechanical stresses on the field and hence the reliability study of these devices is of utmost concern. The performance of model-based methods depends on strong assumptions of the initial values for the parameters and also on the choice of the degradation model. In this work, we propose to use a data-driven method using the feedforward neural network for prognosis of power MOSFET devices with large noise. The experimental data consists of accelerated aging tests done on these devices, extracted from recently published work. The impact on modifying the complexity of the neural network framework on the prognostic metrics such as relative accuracy and computational time are analyzed and quantified. The results demonstrate that the neural network model yields good prediction results even for a highly noisy dataset and also for degradation trends that are strikingly different from the training dataset trend.

Comments on “Highly Biased Linear Condition Method for Separately Extracting Source and Drain Resistance in MOSFETs”

In the above paper, Kim et al. present a method for extracting source and drain resistance values in MOSFETs. We explain how the proposed method corresponds to a particular case of the method already proposed by Ortiz-Conde et al. in a seminal work published in 1994 and generalized two years later, which was not cited in the above-mentioned paper. We call attention to the fact that the absence in Kim’s method of the threshold voltage dependence on body-source voltage and such disregard might eventually lead to significant errors.

6-bit Step Attenuators for Phased-Array System With Temperature Compensation Technique

This letter presents 6-bit differential step attenuators on SiGe BiCMOS for ${K}$ - and Ka -bands with temperature compensation technique. A temperature-variant voltage source (TVVS) is applied to source and drain terminals of the switch MOSFETs. on-state resistance of MOSFETs, therefore, remains stable with temperature variation. With this technique, the root mean square (RMS) attenuation error will be stabilized under different ambient temperatures. Two attenuators for ${K}$ - and Ka -bands are fabricated using 0.13- $\mu \text{m}$ IBM 8XP SiGe BiCMOS process; both attenuators have a maximum attenuation of 31.5 dB with a step of 0.5 dB. The attenuator working at 15–18 GHz exhibits a maximum RMS attenuation error of 0.3 dB from −55 °C to 125 °C, whereas the attenuator working at 19–24 GHz shows a maximum RMS attenuation error of 0.5 dB. To the authors’ best knowledge, for the first time, a TVVS is added to a 6-bit differential step attenuator to achieve consistent attenuation accuracy during thermal variation.

Highly Biased Linear Condition Method for Separately Extracting Source and Drain Resistance in MOSFETs

A highly biased linear current method (HBLCM) for separately extracting source and drain resistance ( ${R}_{S}$ and ${R}_{D}$ ) in MOSFETs is proposed. The technique can be applied to a single device by using simple modeling. Compared to other methods, it provides accurate values of ${R}_{S}$ and ${R}_{D}$ because it considers carrier mobility degradation. The method basically uses linear current versus gate voltage ( ${I}_{\text {DS}} - {V}_{\text {GS}}$ and ${I}_{\text {SD}} - {V}_{\text {GD}}$ ) characteristics before and after the source/drain interchange ( ${I}_{\text {DS}}$ and ${I}_{\text {SD}}$ ). Afterward, by using the traditional Y-function and subsequent resistance modeling in a highly biased linear condition, ${R}_{S}$ and ${R}_{D}$ can be separately extracted. In order to evaluate and verify the accuracy of HBLCM, an external resistor was intentionally connected to a source electrode of a device, and the resulting change in source resistance was detected using the proposed method. Moreover, to demonstrate an application of the proposed method, internal resistance deliberately created by hot-carrier injection (HCI) was linked to a drain electrode, thereby changing drain resistance. The changed drain resistance was also sensed by the HBLCM. Afterward, the HCI-stressed device was cured by electrothermal annealing driven by Joule heating, and the recovery was again clearly observed using the proposed method.

A semi-empirical model of the drain/source resistance for MOSFET

A series resistance model is developed to accurately predict the drain/source resistance of MOSFETs in the ultra submicron regime. The series resistance model is based on the differential resistance concept and the mean value theorem of integrals. Three parameters of the model may be obtained through the multiple linear regression method. In this study, we employ numerical simulation data to fit three parameters for the planar nMOSFETs and nLDD-MOSFETs, of which the substrate doped concentration is $1\times10^{15}\sim~1\times10^{16}{\rm~cm}^{-3}$, and the channel length is 45$\sim$2000 nm. We also obtain a semi-empirical formula with a maximum error of only 9.5%. The theoretical model and calculation results of its semi-empirical formula show that the drain/source resistance is only related to the depth of the drain/source pn junction, resistivity, and length from the channel to the drain/source electrode, and that the influence of the channel length, stack-gate length, and electrode length is negligible. Because the semi-empirical formula is simple, with high precision and a clear physical concept, and allows for easy parameter extraction, it can be used in a characteristic analysis of MOSFETs and circuit simulators.

A Comparisson of Synchronous And Nonsynchronous Boost Converter

Modern electronic systems require resources with high efficiency. The efficiency of direct current to dicrect current converters as a power source can be increased by replacing a diode with MOSFET. The use of MOSFET is expected to reduce power loss as the internal resistance of MOSFET is lower than a diode. To implement the propossed idea, a boost type direct current chopper and TL494 as PWM generator circuit were applied in this work. MOSFET is used in synchronization mode to replace diode at conventional topology of chopper. The proposed circuit and conventional topology were made and their performance were observed. The efficiency of both circuit were compared and analyzed. The result of the experiments showed that the efficiency of converter within MOSFET at synchronization mode is proportional with the increment of duty cycle, while at conventional topology the efficiency remain stable at any duty cycle. Synchronous boost converter is more efficient than nonsynchronous boost converter at duty cycle over than 40%.

A Comparisson of Synchronous and Nonsynchronous Boost Converter

Modern electronic systems require resources with high efficiency. The efficiency of direct current to dicrect current converters as a power source can be increased by replacing a diode with MOSFET. The use of MOSFET is expected to reduce power loss as the internal resistance of MOSFET is lower than a diode. To implement the propossed idea, a boost type direct current chopper and TL494 as PWM generator circuit were applied in this work. MOSFET is used in synchronization mode to replace diode at conventional topology of chopper.. The proposed circuit and conventional topology were made and their performance were observed. The efficiency of both circuit were compared and analyzed. The result of the experiments showed that the efficiency of converter within MOSFET at synchronization mode is proportional with the increment of duty cycle, while at conventional topology the efficiency remain stable at any duty cycle. Synchronous boost converter is more efficient than nonsynchronous boost converter at duty cycle over than 40%.

Two-dimensional physically based semi-analytical model of source/drain series resistance in MOSFETs

In this study, a two-dimensional physically based semi-analytical model of source/drain series resistance in MOSFETs is developed, in which only one parameter needs to be extracted by measurement and the extracted parameter can be repeatedly used when the structure size of the source or drain is changed. The model at the first time separates the resistance into two independent parameters that multiply each other. One is the extracted parameter that is only related to the resistivity. The other one is calculated by the expressions obtained by using the semi-analytical method and Eigen function expansion method, and is only related to the structure size of the source or drain area. The model provides a new approach to solve the resistance problem and matches well with simulation results. It can be used easily to estimate the resistance when the device structure changes in device design.

MW-scale ICRF plasma heating using IGBT switches in a multi-pulse scheme

Solid-state silicon switches are cheap and reliable option for 1–10 MHz RF power sources, required for plasma ion cyclotron RF heating (ICRF). The large `on' resistance of MOSFET and similar devices limits their power delivery to a few tens of kW per switch. Low resistivity devices, such as IGBT, suffer from large `off' switching time, which limits their useful frequency range and increases the power dissipated in the switch. Here we demonstrate more than 0.8 MW circulated RF power at 2 MHz using only three high voltage IGBT switches. The circuit uses the fast `on' switching capability of the IGBTs to generate high-Q pulse train. This operation mode also simplifies the measurement of RF coupling between the antenna and the plasma.

Accurate Extraction of Effective Gate Resistance in RF MOSFET

This paper describes the gate electrode resistance of MOSFET and non-quasi-static (NQS) effect for RF operation. The vertical current paths between the silicide layer and poly-silicon are considered in the gate electrode. The vertical current paths are not effective in long-channel devices, but become more significant in short-channel devices. The gate resistance including vertical current paths can reproduce the practical RF characteristics well. By careful separation of the above gate electrode resistance and the NQS effect, the small-signal gate-source admittance can be analyzed with 130-nm CMOS process. Elmore constant (κ) of the NQS gate-source resistance is about five for long-channel devices, while it decreases down to about three for short-channel devices.

The Key Parameter Modeling of SiC MOSFET

This thesis mainly analysed the internal relations between parameters of SiC MOSFET and its dynamic and static characteristics respectively. And furthermore, a new method for modeling of SiC MOSFET based on PSpice was proposed in this paper. By introducing voltage’s controlling for voltage source E, we can compensate and correct the difference between PSpice default value of gate threshold voltage and actual value. At the same time, we can adopt two different junction capacitance models to describe the changes of junction capacitance which were brought about by the difference of the terminal voltage. In the meanwhile, there are newly increased source-drain resistance of MOSFET and gate resistance with the temperature change of variable temperature sub models. New models are able to fully and accurately reflect SiC MOSFET’s static and dynamic characteristics. Moreover, it provides an important foundation for switch process analysis of SC MOSFET, loss calculation and main circuit design. The fact that the experimental testing result is highly coincident with the simulation results verifies the correctness and accuracy of the models.

A 4.6 GHz cascade switched biasing LC–QVCO using source-body resistor

This paper presents a 4.6 GHz LC quadrature voltage-controlled oscillator (QVCO) in which the phase noise performance is improved by two methods: cascade switched biasing (CSB) technique and source-body resistor. The CSB topology can reduce the resonator loss caused by MOSFET resistance. Meanwhile, it can maintain the benefits of conventional switched biasing technique. The source-body resistors are utilized to reduce the noise contribution of the substrate related to the cross coupled MOSFETs. The proposed QVCO has been implemented in standard 0.18 μm CMOS technology. With the two methods mentioned above, it consumes 4.9 mW under 1 V voltage supply and achieves a phase noise of ?120.3 dBc/Hz at 1 MHz frequency offset from the carrier of 4.56 GHz. The figure of merit is 186.5 dBc/Hz and the tuning range is from 4.2 G to 5 GHz (17.3 %). When the QVCO operates at 0.8 V voltage supply, the power consumption is 2.88 mW and the phase noise is ?115.7 dBc/Hz at 1 MHz frequency offset from the carrier of 4.58 GHz.

A self-consistent extraction procedure for source/drain resistance in MOSFETs

A new method to determine source/drain series resistance has been developed for MOSFETs operated in linear region. The source/drain resistance ( R SD ) is gate-bias dependent. Channel length reduction (Δ L) is extracted at low gate bias and chosen to be constant. All parameters extracted in this method are assumed to be independent of mask channel length for model simplicity. The method has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185 μm. The extracted parameters are consistent with the assumptions and have been validated by measured I– V characteristics.

Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method

The separate extraction of asymmetric source (RS) and drain (RD) resistances caused by the variations in the layout, process, and device degradation is important in the practical modeling and characterization of MOSFETs and their integrated circuits. We propose a simple “parasitic junction current method” (PJCM) for the separate extraction of RS, RD, and RSUB (substrate resistance) in MOSFETs. We applied the proposed PJCM to n-channel MOSFETs with different W/L combinations and verified its usefulness in the robust extraction of RS, RD, and RSUB.

Extraction of bias-dependent parasitic source/drain resistance in MOSFETs with an advanced mobility model

We present a new method to extract gate-bias-dependent source/drain resistance in MOSFETs. The extraction starts from a simple mobility model, but a more sophisticated mobility model is incorporated afterward. The method provides a convenient way to extract the source/drain resistance as well as parameters in a sophisticated mobility model. The extracted parameters in the mobility model vary with channel length. To satisfy some device modeling work where parameters independent of channel length are desirable, we also develop another technique so that a single set of parameters is obtained and is applicable to all channel lengths. The extraction techniques are useful for submicron MOSFETs without going through complicated procedure.