Residue Number System Research Articles

A Hybridized Honey Encryption for Data Security using Residue Number System

Different encryption algorithms such as Advanced Encryption Standard (AES), Rivest, Shamir, Adleman (RSA) were proposed to protect the privacy of the data. However, most of these existing methods are vulnerable to a brute-force attack because the cipher text remains unintelligible until the original data is found. Consequently, this problem prompted researchers to introduce honey encryption (HE). HE helps to withstand the vulnerability of the encryption algorithms in brute force attacks making transmitted data more secure and efficient. Hence to reduce processing time we proposed a hybridized HE with Residue Number System. Traditional Moduli Set {2n-1, 2n, 2n+1} was used to generate the Key while Chinese Remainder Theorem (CRT), and HE technique were used for decrypting the data, based on the Distribution Transformation Decoder. Thus, anytime an attacker tries to access the data, so long the length of the guessed key is the same as the original key, the HE algorithm will generate meaningful but fake data, this helps to deter an attacker from further threat. The result showed that the proposed system was able to withstand brute force attacks with less processing time compared to other systems. N-values for the moduli set used were varied against encryption and decryption time. Comparing the obtained results with the existing system, the proposed system processing time was faster and more secure.

Application of Residue Number Systems in enhancing the transmission of secured videos

Application of Residue Number Systems in enhancing the transmission of secured videos

A Generalized Residue Number System Design Approach for Ultralow-Power Arithmetic Circuits Based on Deterministic Bit-Streams

The peak power consumption has become an important concern in the hardware design process of some of today’s applications, such as Energy Harvesting (EH) and Bio-Implantable (BI) electronic devices. The limited peak harvested power in EH devices and heating concerns in BI devices are the main reasons for power control’s importance in these devices. This paper proposes a generalized design approach for ultra-low-power arithmetic circuits. The proposed circuits are based on Residue Number System (RNS) combined with deterministic bit-streams. The resulting circuits can be used in systems with a restricted power budget. We suggest several approaches to design generic hardware-efficient adders, multipliers, multiply-accumulate units (MAC), forward converters (FC), and reverse converters (RC). Using the proposed approach, designing these components for any moduli of the RNS can be performed through simple bit-width adjustments in the circuits. The synthesis results show that the proposed adder achieves, on average, 69% and 2% lower area compared to the bit-serial and a state-of-the-art RNS adder, respectively. Furthermore, the proposed multiplier outperforms the bit-serial, interleaved, and a state-of-the-art design for multiplying RNS numbers by, on average, 57%, 60%, and 77% in terms of power consumption, respectively. The efficiency of our approach is shown via two essential applications, digital signal processing and machine learning. We implement an FFT engine using the proposed method. Compared to prior RNS implementations, our design achieves 47% lower power consumption. We also implement a CNN accelerator’s Processing Element (PE) with the proposed computation elements. Our design provides considerable speedup and lower power consumption compared to a state-of-the-art ultra-lower-power design.

Feature selection in intrusion detection systems: a new hybrid fusion of Bat algorithm and Residue Number System

ABSTRACT This research introduces innovative approaches to enhance intrusion detection systems (IDSs) by addressing critical challenges in existing methods. Various machine-learning techniques, including nature-inspired metaheuristics, Bayesian algorithms, and swarm intelligence, have been proposed in the past for attribute selection and IDS performance improvement. However, these methods have often fallen short in terms of detection accuracy, detection rate, precision, and F-score. To tackle these issues, the paper presents a novel hybrid feature selection approach combining the Bat metaheuristic algorithm with the Residue Number System (RNS). Initially, the Bat algorithm is utilized to partition training data and eliminate irrelevant attributes. Recognizing the Bat algorithm's slower training and testing times, RNS is incorporated to enhance processing speed. Additionally, principal component analysis (PCA) is employed for feature extraction. In a second phase, RNS is excluded for feature selection, allowing the Bat algorithm to perform this task while PCA handles feature extraction. Subsequently, classification is conducted using naive bayes, and k-Nearest Neighbors. Experimental results demonstrate the remarkable effectiveness of combining RNS with the Bat algorithm, achieving outstanding detection rates, accuracy, and F-scores. Notably, the fusion approach doubles processing speed. The findings are further validated through benchmarking against existing intrusion detection methods, establishing their competitiveness.

A novel sign detection method in residue number system based on Chinese remainder theorem with fractional values

Sign detection is a non-modular operation in the residue number system (RNS). It requires the calculation of the number positional characteristic represented in the RNS. This work proposes a new sign detection method based on the Chinese Remainder Theorem (CRT) with fractional values implemented using the Wallace tree and the modified Kogge-Stone adder. Hardware modelling on FPGA for the proposed method shows that it provides 1.3 – 36.3 times less hardware costs than the other state-of-the-art (SOTA) methods, and for ASIC modelling the proposed method provides 1.14 – 35.74 times less hardware costs than the other SOTA methods. The presented sign detection method can be helpful in RNS-based devices in implementing comparison and division operations, providing an extension of the RNS application in areas such as cryptography, machine learning, and digital signal processing.

Algorithm for Determining the Optimal Weights for the Akushsky Core Function with an Approximate Rank

In this paper, a study is carried out related to improving the reliability and fault tolerance of Fog Computing systems. This work is a continuation of previous studies. In the past, we have developed a method of fast operation for determining the sign of a number in the Residue Number System based on the Akushsky Core Function. We managed to increase the efficiency of calculations by using the approximate rank of a number. However, this result is not final. In this paper, we consider in detail the methods and techniques of the Akushsky Core Function. During research, it was found that the so-called weights can be equal to random variables. Based on the data obtained, we have developed a method for determining the optimal weights for the Akushsky Core Function. The result obtained allows you to obtain a performance advantage due to the preliminary identification of optimal weights for each set of moduli.

FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

The residue number system is widely used in applications such as communication systems, cryptography, digital filters, digital signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both modulo (2n − 1) and modulo (2n + 1) multipliers using the same hardware structure with only one control signal. A novel modulo (2n ± 1) multiplier based on radix-4 Booth encoding is proposed that can achieve superior performance, with low power, fast operation, high area efficiency, and low area-delay product (ADP) and power-delay product (PDP) compared with similar modified Booth-encoding methods. In addition, by integrating the separate modulo functions of the modulo (2n − 1) multiplier and modulo (2n + 1) multiplier into a single multifunction modulo (2n ± 1) multiplier, the proposed method can save up to 52.59% (n = 16) of hardware area, up to 5.45% (n = 32) of delay time, up to 49.05% (n = 16) of dynamic power, up to 50.92% (n = 32) of ADP, and up to 50.02% (n = 32) of PDP compared with the original separate circuits merged together. Furthermore, the operation ranges of the multiplicand and multiplier of the proposed modulo (2n + 1) multiplier and modulo (2n − 1) multiplier are {0, 2n + 1} and {0, 2n}, respectively, which are wider than for other reported hardware structures. The hardware area, power consumption, and delay time are simulated and verified using Verilog HDL and Xilinx FPGA (Field Programmable Gate Array) Vivado tools. The Xilinx Artix-7 XC7A35T-CSG324-1 FPGA chipset is adopted in the proposed work.

Design of reverse converters for the general RNS 3-moduli set {2k, 2n − 1, 2n + 1}

This paper presents a new design method of the reverse (residue-to-binary) converter for the flexible 3-moduli residue number system (RNS) set { 2^k, 2^n-1, 2^n+1 }, where k and n are a pair of arbitrary integers ge 2. The basic equation of the reverse converter is formulated in two alternative forms, each of which consists of two separate parts: one depending on input variables of the converter, and the other being a single constant. The constant can be either added inside the reverse converter or shifted out to the residue datapath channels, in most cases at no hardware cost or extra delay. From the set of basic functions, which are essentially different than those of the only two known general converters proposed for this moduli set, four versions of a converter can be designed for any pair of k and n. Experimental results obtained using the commercial 65-nm low-power design kit and industrial synthesis tools for all dynamic ranges from 8 to 40 bits suggest that, compared to the state-of-the-art designs, at least one version of the newly proposed converters is superior w.r.t. delay, power consumption, and area, for all dynamic ranges considered. The savings for the best versions (these with constants moved to the datapath channels) are up to 12.7% for the area and from 2.5% to 14% (5.8 % on average) for the delay, while the power consumption is reduced up to 23.2% (5.6% on average).

Residue number systems with six modules and efficient circuits based on power-of-two diagonal modulus

The paper suggests an algorithm for finding Residue Number Systems (RNS) with six modules (6-tuples) with the Sum of Quotients SQ=2k for some positive integer k. It is shown that there are exactly thirteen such 6-tuples (m1,…,m6) with m1+m2≤10000 and m3+m4≤m5+m6≤10000 and investigated the three smallest among them, namely (5,2399,7,11,23,1691), (47,293,25,193,41,257), and (23,1433,13,29,681,821), having k=34, 36, and 40, respectively. The hypothesis is that such RNS allow efficient hardware implementations of non-modular operations — division, sign detection, comparison of numbers, and reverse conversion from the point of hardware resource usage and balancedness. The special case SQ=2k allows a significant simplification of these operations and increased efficiency of hardware implementations. Hardware modeling of circuits based on the above 6-tuples that implement magnitude comparison and reverse RNS to binary conversion (reverse conversion) is presented. The suggested magnitude comparison and reverse conversion devices, which operate with the six modules, are built using the methodology and values of the diagonal function, carry-save, and Kogge-Stone adders. The results of FPGA-based hardware modeling and the theoretical parameters of devices calculated using the unit-gate model are compared with state-of-the-art approaches. The unit-gate model showed that the use of the proposed circuits allows us to reduce the area by 17.82%–50.81% and the delay by 1.56%–97.76% for the implementation of the magnitude comparison, and to reduce the delay by 2.80%–95.03% for the implementation of reverse conversion. The FPGA synthesis also showed that the new design has reduced the area and delay by 46.96%–86.80% and 7.15%–47.65%, respectively, for the implementation of magnitude comparison and reduced the delay by 13.63%–81.53% for the implementation of reverse conversion. It is shown that a proposed technique to measure the RNS balance can adequately reflect differences in the RNS performance.

Round efficient privacy-preserving federated learning based on MKFHE

Federated learning (FL) was created with the intention of enabling collaborative training of models without the need for direct data exchange. However, data leakage remains an issue in FL. Multi-Key Fully Homomorphic Encryption (MKFHE) is a promising technique that allows computations on ciphertexts encrypted by different parties. MKFHE’s aptitude to handle multi-party data makes it an ideal tool for implementing privacy-preserving federated learning.We present a multi-hop MKFHE with compact ciphertext. MKFHE allows computations on data encrypted by different parties. In MKFHE, the compact ciphertext means that the size of the ciphertext is independent of the number of parties. The multi-hop property means that parties can dynamically join the homomorphic computation at any time. Prior MKFHE schemes were limited by their inability to combine these desirable properties. To address this limitation, we propose a multi-hop MKFHE scheme with compact ciphertext based on the random sample common reference string(CRS). We construct our scheme based on the residue number system (RNS) variant CKKS17 scheme, which enables efficient homomorphic computation over complex numbers due to the RNS representations of numbers.We construct a round efficient privacy-preserving federated learning based on our multi-hop MKFHE. In FL, there is always the possibility that some clients may drop out during the computation. Previous HE-based FL methods did not address this issue. However, our approach takes advantage of multi-hop MKFHE that users can join dynamically and constructs an efficient federated learning scheme that reduces interactions between parties. Compared to other HE-based methods, our approach reduces the number of interactions during a round from 3 to 2. Furthermore, in situations where some users fail, we are able to reduce the number of interactions from 3 to just 1.

Fast Operation of Determining the Sign of a Number in RNS Using the Akushsky Core Function

This article presents a study related to increasing the performance of distributed computing systems. The essence of fog computing lies in the use of so-called edge devices. These devices are low-power, so they are extremely sensitive to the computational complexity of the methods used. This article is aimed at improving the efficiency of calculations while maintaining an appropriate level of reliability by applying the methods of the Residue Number System (RNS). We are investigating methods for determining the sign of a number in the RNS based on the core function in order to develop a new, fast method. As a result, a fast method for determining the sign of a number based on the Akushsky core function, using approximate calculations, is obtained. Thus, in the course of this article, a study of methods for ensuring reliability in distributed computing is conducted. A fast method for determining the sign of a number in the RNS based on the core function using approximate calculations is also proposed. This result is interesting from the point of view of nebulous calculations, since it allows maintaining high reliability of a distributed system of edge devices with a slight increase in the computational complexity of non-modular operations.

An Application of Residue Number System (RNS) to Molecular Biology

George Gamow introduced the mathematical angle that led to a better understanding of the number of possible codons of the genetic code. This builds a harmonious relationship between mathematics and molecular biology. Although very unsuccessful in his quest to provide the representation of the genetic code, with the diamond code, but his mathematical postulation of the genetic code being a 4 by 4 by 4 codon representation of 64 codons was correct. Bioinformatics ascribe digits to nitrogenous bases, binary digits, but there has been proponents for a quaternary number system representation of the genetic code since the code is made of the four (4) nitrogenous bases. The unique representation of Gamow offers the opportunity to represent the genetic code as a 3-moduli set RNS. This sets up further considerations of the genetic code (code of life) in the field of Residue Number System (RNS). AnRNS-Genetic code has the potential of opening new extraordinary vistas of potential progress in contemporary molecular biology. This work explores the feasibility of RNS as a number system of choice for generating the genetic code and further respond to the quest for a quaternary number system for the genetic code.

Residue Number System (RNS) Sequence Comparison and Mutation (Error) Analysis

The genetic code may be generated using the Residue Number System (RNS). This achievement demonstrates the viability of protein synthesis. The genetic codes occupy RNS digits and enable sequence comparison as well as further analysis of biological flaws known as mutations. In this research work two mRNA reading frames (strings) are considered as strings of RNS digits. Triplets of these residue number digits constitutes an amino acids and chains of these triplets make up polypeptides, proteins. These digits are compared and single digits errors introduced, these errors mimic biological errors (mutations). The types of errors (mutations) that are manifested between the two reading frames, original and mutant, are detected and reported.

Design and Performance Analysis of RNS-Based Reconfigurable FIR Filter for Noise Removal in Speech Signals Applications

In DSP solutions, the Residual Number System with Two's Complement systems is the most commonly utilized system for building low-power and high-throughput programmable Finite Impulse Response filters. It would be done by creating FIR filters in the Residual Number organization and 2's Enhance scheme by comparing the results to the current assert. The RNS based on FIR filter architecture reduces power consumption while allowing the device to operate at 150 MHz without increasing its size significantly. In case of memory and latency reduction, the implementations of the Residual Number System and 2's Complement System must be able to obtain and decode signals with fewer physical servers for every clock signal. The principal idea of this proposed model is to provide data bits with larger sizes for RNS-based multiplier and delayed wavelet LMS (DWLMS) that operates at speed high with premised reconfigurable FIR via forward and reverse conversions that don't produce as much power output and size as reflective thinking. The Application Specific Integrated Circuit will be designed and integrated for 32 nm technology. The proposed design addresses the four essential parameter optimization, such as power, area, and timing, using the Residual Number System, which is superior to Two's Complement System. According to the findings, there is a 13 percent reduction in power, a 21 % enhancement in area, and a 13 % enhance in throughput.

Efficient Sign-Detection-Scheme Using Modular Computation Technique for the Moduli Set {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1, 2<sup>(n+1)</sup>-1, 2<sup>2n</sup>-5}

In computer arithmetic, one of the most important things to consider in hardware design is the ability of the system to detect and display numbers with their signs. This when properly managed will reduce errors and ensure hardware reliability. But interestingly, detecting and knowing the sign of a residue number during arithmetic operation is very difficult. Magnitude Comparison, Scaling and Number conversions are some of the other difficult operations in Residue Number System (RNS). Unlike the weighted number system, it is even extremely difficult to determine the sign of a number in an RNS architecture thereby hampering the full implementation RNS in general purpose computing. In this paper, an efficient sign detection algorithm for detecting the sign of a number in an RNS architecture is presented. In formulating the algorithms, X maximum, (X_max) is computed from the Dynamic Range, M=∏^k_i=1(m_i). Modular Computation Technique is employed as a converter to compute X from the residues (r₁, r₂, r₃) with respect to a given moduli set, say S= {m₁, m₂ ..., m_n}. X is positive if X-X_max<0 otherwise X is negative and the actual value is this case is computed as X-M. The moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2⁽ⁿ⁺¹⁾-1, 2²ⁿ-5} is used for the system design implementation and for numerical illustrations. It is observed that the scheme effectively detects the sign of RNS numbers and theoretical analysis showed that simple hardware resources and low-power modular adders are used in the design. It is also observed that the scheme when implemented practically can help project RNS to be used in general purpose computing.

Residue to Binary Converter for a Four Moduli Set

Abstract: Due to issues with conventional number systems (binary), such as the carry propagation issue, which reduces the performance of hardware computing systems, residue number systems (RNS) have gained popularity. Residue to binary conversion speed and complexity, as well as the speed of the internal RNS arithmetic unit, all affect how well a residue number system (RNS) performs. We have included a number of studies on the recognition of RNS Number Systems and Residue to Binary Converter Systems for various moduli sets in this paper. Additionally, we implemented a model and calculated the value of LUT’S, Slices and other components within it.

Support vector machines implementation over integers modulo-M and Residue Number System

In low-power hardware implementations for classification algorithms, it is often essential to use physical resources efficiently. In this sense, the use of modulo-M integer operations instead of floating-point arithmetic, can lead to better performance, especially when M represents the dynamic range of an arithmetic block of the Residue Number System (RNS) [1,2]. Following this premise, this work is aiming to provide a methodology for implementing a classifier, specifically a Support Vector Machine (SVM) [3], using modulo-M integers and proposing a method for the use of Residue Number System.

An improved residue multiplier using Montgomery modular multiplication

Implementing cryptosystems using the residue number system (RNS) requires many balanced equally-wide residue channels. The generic residue multiplier has a significant impact on the residue balance. Improving the residue multiplier delay affects the RNS efficiency. The Montgomery reduction is used for the residue generation in the auto-scale multiplier method, where its operations are merged to reduce residue generation delay. The synthesis result shows the proposed work delay has improved by 36%, 41%, and 29% for three channel widths of 16, 32, and 64-bit compared to the previous relevant work. Moreover, the area consumption has reduced by about 40%.

Area-Efficient digital filtering based on truncated multiply-accumulate units in residue number system [formula omitted

High resource consumption of digital filtering devices is one of the main practical problems of digital signal processing. Parallel data processing is one of the most effective approaches to improve the quantitative characteristics of such devices. This paper proposes a method for filtering signals using Truncated Multiply-and-Accumulate units (TMAC) in the residue number system (RNS) using moduli of a special type 2n-1,2n,2n+1. These moduli reduced hardware costs and power consumption compared to state-of-the-art approaches for a 32-bit RNS filter by up to 23% and up to 22.3%, respectively, with a delay increase of 131%. The proposed approach allowed to reduce the device area by up to 14% with comparable energy expended for a 48-bit RNS filter, but the device delay increased by 81%. The results obtained open up the possibility of creating area-efficient and power-efficient devices.

Measuring 3- and 4-Moduli Sets Delay Per Bit in Residue Number System: A Survey

Given the efficiency of the residue number system in high-speed and low-power applications, a wide variety of moduli sets have been introduced in the literature. Selecting an appropriate moduli set is one of the most important issues of using a residue number system. Moduli sets can be evaluated by several factors such as dynamic range, balanced channels, fast and low-power modular operations, and efficient reverse converter. In this paper, 3- and 4-moduli sets are separately reviewed and compared from a different perspective. Furthermore, the most efficient 3- and 4-moduli sets are suggested. A new parameter for average delay comparison is introduced, which shows the delay of every bit in the dynamic range providing a fair comparison of moduli sets with different numbers of moduli. Our comparison showed that either balanced channels or the delay of computations are essential factors for designing an efficient new moduli set.