Residue Number System Multipliers Research Articles

High Precision Multiplier for RNS {2n−1,2n,2n+1}

The Residue Number System (RNS) is a non-weighted number system. Benefiting from its inherent parallelism, RNS has been widely studied and used in Digital Signal Processing (DSP) systems and cryptography. However, since the dynamic range in RNS has been fixed by its moduli set, it is hard to solve the overflow problem, which can be easily solved in Two’s Complement System (TCS) by expanding the bit-width of it. For the multiplication in RNS, the traditional way to deal with overflow is to scale down the inputs so that the result can fall in its dynamic range. However, it leads to a loss of precision. In this paper, we propose a high-precision RNS multiplier for three-moduli set 2n−1,2n,2n+1, which is the most used moduli set. The proposed multiplier effectively improves the calculation precision by adding several compensatory items to the result. The compensatory items can be obtained directly from preceding scalers with little extra effort. To the best of our knowledge, we are the first one to propose a high-precision RNS multiplier for the moduli set 2n−1,2n,2n+1. Simulation results show that the proposed RNS multiplier can get almost the same calculation precision as the TCS multiplier with respect to Mean Square Error (MSE) and Signal-to-Noise Ratio(SNR), which outperforms the basic scaling RNS multiplier about 2.6–3 times with respect to SNR.

Area-Power Efficient Modulo $2^{n}-1$ and Modulo $2^{n}+1$ Multipliers for $\{2^{n}-1, 2^{n}, 2^{n}+1\}$ Based RNS

Residue Number System (RNS) is often adopted to implement long and repetitive multiplications of cryptographic and signal processing algorithms. To sustain the competitive advantages of RNS over two's complement system in pervasive computing platforms, the hardware cost of parallel modulo arithmetic operations must be lowered. In this paper, new low power and low area modulo multipliers for the well-established {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> , 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> + 1} based RNS are proposed. The proposed modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -1 and modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> + 1 multipliers are based on the radix-8 Booth encoding technique. The requisite hard multiples in the critical path are generated by fast customized parallel-prefix adders. In the proposed modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 multiplier, the number of partial products is lowered to ⌊ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> /3⌋ + 1, which is around 33% reduction over radix-4 Booth encoded multiplier for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> = 32-64 . For modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> + 1 multiplication, the aggregate bias due to the hard multiple and the modulo-reduced partial product generations is composed of multiplier-dependent dynamic bias and multiplier-independent static bias. Both biases have been reduced by properties of modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> + 1 arithmetic and merged into only three <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -bit words. Consequently, the total number of partial products in the proposed modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> + 1 multiplier is given by ⌊ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> /3⌋ + 6, which is 11% and 35% reduction over radix-4 Booth encoded multiplier for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> = 32 and 64, respectively. From synthesis results for {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> , 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> + 1} based RNS multipliers constructed from different modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 and modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> + 1 multipliers, our proposed modulo multipliers save 4%-40% and 24%-34% area as well as 21%-40% and 7%-19% total power dissipation over radix-4 Booth encoded and non-encoded modulo multipliers, respectively. These results are well correlated with the theoretical estimation based on the normalized area model.

Radix-8 Booth Encoded Modulo $2 ^{n} -1$ Multipliers With Adaptive Delay for High Dynamic Range Residue Number System

A special moduli set Residue Number System (RNS) of high dynamic range (DR) can speed up the execution of very-large word-length repetitive multiplications found in applications like public key cryptography. The modulo 2n-1 multiplier is usually the noncritical datapath among all modulo multipliers in such high-DR RNS multiplier. This timing slack can be exploited to reduce the system area and power consumption without compromising the system performance. With this precept, a family of radix-8 Booth encoded modulo 2n-1 multipliers, with delay adaptable to the RNS multiplier delay, is proposed. The modulo 2n-1 multiplier delay is made scalable by controlling the word-length of the ripple carry adder, k employed for radix-8 hard multiple generation. Formal criteria for the selection of the adder word-length are established by analyzing the effect of varying k on the timing of multiplier components. It is proven that for a given n, there exist a number of feasible values of k such that the total bias incurred from the partially-redundant partial products can be counteracted by only a single constant binary string. This compensation constant for different valid combinations of n and k can be precomputed at design time using number theoretic properties of modulo 2n-1 arithmetic and hardwired as a partial product to be accumulated in the carry save adder tree. The adaptive delay of the proposed family of multipliers is corroborated by CMOS implementations. In an RNS multiplier, when the critical modulo multiplier delay is significantly greater than the noncritical modulo 2n-1 multiplier delay, k = n and k = n /3 are recommended for n not divisible by three and divisible by three, respectively. Conversely, when this difference diminishes, k is better selected as n /4 and n /6 for n not divisible by three and divisible by three, respectively. Our synthesis results show that the proposed radix-8 Booth encoded modulo 2n-1 multiplier saves substantial area and power consumption over the radix-4 Booth encoded multiplier in medium to large word-length RNS multiplication.

A low-complexity combinatorial RNS multiplier

A novel very large scale integration architecture and the corresponding design methodology for a combinatorial adder-based residue number system (RNS) multiplier are presented in this paper. The proposed approach to residue multiplier design, exploits the nonoccurring combinations of input bits to reduce the number of 1-bit full adders (FAs) required to compose an RNS multiplier. In particular, input bits which cannot be simultaneously asserted for any input residue value are organized into couples or triplets, which can be processed by OR gates instead of 1-bit adders, therefore reducing the RNS multiplier complexity. By comparing the performance and hardware complexity of the proposed residue multiplier to previously reported designs, it is found that the introduced architecture is more efficient in the area/spl times/time product sense. In fact, it is shown that a performance improvement in excess of 80% can be achieved in certain cases.

RNS cellular arrays

The residue number system (RNS) is receiving increased attention due to its ability to support high-speed arithmetic. To convert this body of knowledge into practice, custom VLSI devices will be needed. In this work, procedures by which a set of identical RNS-VLSI chips of small wordlength can be integrated into a wide wordlength system are presented. The mathematical structure of such an interconnected system of RNS adders and multipliers is reported. With these new results, custom VLSI devices may for the first time, impact RNS design.