Abstract
The residue number system (RNS) is receiving increased attention due to its ability to support high-speed arithmetic. To convert this body of knowledge into practice, custom VLSI devices will be needed. In this work, procedures by which a set of identical RNS-VLSI chips of small wordlength can be integrated into a wide wordlength system are presented. The mathematical structure of such an interconnected system of RNS adders and multipliers is reported. With these new results, custom VLSI devices may for the first time, impact RNS design.
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