Residue Number System Research Articles

Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder

Residue Number System has to carry free operation and its various applications like digital signal processing, multimedia, security purpose, and medical perception. Removes of the redundant logic operation require the group carry selection logic which is dependent on Parallel Prefix Adder design. Therefore the logic operation of the preprocessing unit of PPA is simplified form to save logic resources. This modified parallel prefix adder consumes less area as compared to the existing design. In this paper, we propose the parallel architecture based on a parallel prefix tree is helpful for computation at higher speed operation. The reported design consumes 24.1% more area and 26.4% more power compare to THE proposed parallel prefix adder design. The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2n+1 adder structure is presented. A presented modulo adder design using the proposed parallel prefix adder and improved carry computation used in the previously proposed design. The proposed diminished-1 modulo (2n +1) adder design shows a 24.5% saving in area-delay-product (ADP).

An Evaluation of Power Side-Channel Resistance for RNS Secure Logic

In this paper, residue number system (RNS) based logic is proposed as a protection against power side-channel attacks. Every input to RNS logic is encrypted as a share of the original input in the residue domain through modulus values. Most existing countermeasures enhance side-channel privacy by making the power trace statistically indistinguishable. The proposed RNS logic provides cryptographic privacy that also offers side-channel resistance. It also offers side-channel privacy by mapping different input bit values into similar bit encodings for the shares. This property is also captured as a symmetry measure in the paper. This side-channel resistance of the RNS secure logic is evaluated analytically and empirically. An analytical metric is developed to capture the conditional probability of the input bit state given the residue state visible to the adversary, but derived from hidden cryptographic secrets. The transition probability, normalized variance, and Kullback–Leibler (KL) divergence serve as side-channel metrics. The results show that our RNS secure logic provides better resistance against high-order side-channel attacks both in terms of power distribution uniformity and success rates of machine learning (ML)-based power side-channel attacks. We performed SPICE simulations on Montgomery modular multiplication and Arithmetic-style modular multiplication using the FreePDK 45 nm Technology library. The simulation results show that the side-channel security metrics using KL divergence are 0.0204 for Montgomery and 0.0020 for the Arithmetic-style implementation. This means that Arithmetic-style implementation has better side-channel resistance than the Montgomery implementation. In addition, we evaluated the security of the AES encryption with RNS secure logic on a Spartan-6 FPGA Board. Experimental results show that the protected AES circuit offers 79% higher resistance compared to the unprotected AES circuit.

Designing of fault-tolerant computer system structures using residue number systems

AbstractThis article discusses computing systems that operate in residue number systems (RNSs). The main direction of improving computer systems (CSs) is increasing the speed of implementation of arithmetic operations and the reliability of their functioning. Encoding data in RNS solves the problem of optimal redundancy, i.e., the creation of such computing systems provides maximum reliability with restrictions on weight and size characteristics. This article proposes new structures of fault-tolerant CSs operating in RNS in the case of the application with an active fault-tolerant method. The use of the active fault-tolerant method (dynamic redundancy) in the RNSs provides higher reliability. In addition, with an increase in the digits of CSs, the efficiency of using the proposed structures increases.

Secured Paillier Homomorphic Encryption Scheme Based on the Residue Number System

Secured Paillier Homomorphic Encryption Scheme Based on the Residue Number System

Multiple-precision sparse matrix–vector multiplication on GPUs

Sparse matrix–vector multiplication (SpMV) appears in many application domains, and performance is the key consideration when implementing SpMV kernels. At the same time, accuracy is also important because rounding errors can drastically change the computed result. Multiple-precision arithmetic is a common approach to improve the accuracy of results. In this paper, we implement and evaluate multiple-precision SpMV kernels in the CSR, JAD, ELLPACK, and DIA matrix storage formats for graphics processing units. In the proposed implementation, the matrix is represented in double precision, while the input and output vectors are in multiple precision and internal computations are also performed in multiple precision. Our underlying floating-point arithmetic algorithms are based on the residue number system, which is attractive because of its carry-free nature and provides an arbitrary level of precision determined by the set of moduli that comprise the base of the system. In particular, we apply sets from 8 to 64 moduli, reaching precision values from 106 to 848 bits, and demonstrate how higher precision reduces the rounding errors in the SpMV kernel. We also conduct a thorough analysis of the CSR kernel in terms of roofline performance, occupancy and memory bandwidth, and evaluate the performance and memory consumption for all the proposed kernels. Numerical experiments on matrices from real-world applications show that ELLPACK offers the highest performance in many examples, while JAD is a good trade-off between performance and space requirements. Furthermore, our proposed kernels in general substantially improve the efficiency of sparse matrix–vector multiplication compared to implementations built on top of existing multiple-precision CUDA libraries. Finally, we integrate the multiple-precision SpMV into a preconditioned conjugate gradient linear solver and identify test cases where our implementation exhibits superior convergence and numerical robustness.

An Efficient Parallel Reverse Conversion of Residue Code to Mixed-Radix Representation Based on the Chinese Remainder Theorem.

In this paper, we deal with the critical problems in residue arithmetic. The reverse conversion from a Residue Number System (RNS) to positional notation is a main non-modular operation, and it constitutes a basis of other non-modular procedures used to implement various computational algorithms. We present a novel approach to the parallel reverse conversion from the residue code into a weighted number representation in the Mixed-Radix System (MRS). In our proposed method, the calculation of mixed-radix digits reduces to a parallel summation of the small word-length residues in the independent modular channels corresponding to the primary RNS moduli. The computational complexity of the developed method concerning both required modular addition operations and one-input lookup tables is estimated as , where k equals the number of used moduli. The time complexity is modular clock cycles. In pipeline mode, the throughput rate of the proposed algorithm is one reverse conversion in one modular clock cycle.

An Efficient Method for Comparing Numbers and Determining the Sign of a Number in RNS for Even Ranges

Fully Homomorphic Encryption (FHE) permits processing information in the form of ciphertexts without decryption. It can ensure the security of information in common technologies used today, such as cloud computing, the Internet of Things, and machine learning, among others. A primary disadvantage for its practical application is the low efficiency of sign and comparison operations. Several FHE schemes use the Residue Number System (RNS) to decrease the time complexity of these operations. Converting from the RNS to the positional number system and calculating the positional characteristic of a number are standard approaches for both operations in the RNS domain. In this paper, we propose a new method for comparing numbers and determining the sign of a number in RNS. We focus on the even ranges that are computationally simple due to their peculiarities. We compare the performance of several state-of-art algorithms based on an implementation in C++ and relatively simple moduli with a bit depth from 24 to 64 bits. The experimental analysis shows a better performance of our approach for all the test cases; it improves the sign detection between 1.93 and 15.3 times and the number comparison within 1.55–11.35 times with respect to all the methods and configurations.

Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases

This paper presents a new architecture to perform modular multiplication using Montgomery multiplication in Residue Number System (RNS). Two new balanced four-moduli RNS bases are selected, and the process of RNS Montgomery multiplication, including the required RNS to RNS conversions, is designed and implemented. Field-programmable gate array (FPGA) implementation using the adder-based residue/binary to binary/residue converters and ROM-free in the pipelined architecture has achieved better performance compared to the state-of-the-art works in literature.

Improved Modular Division Implementation with the Akushsky Core Function

The residue number system (RNS) is widely used in different areas due to the efficiency of modular addition and multiplication operations. However, non-modular operations, such as sign and division operations, are computationally complex. A fractional representation based on the Chinese remainder theorem is widely used. In some cases, this method gives an incorrect result associated with round-off calculation errors. In this paper, we optimize the division operation in RNS using the Akushsky core function without critical cores. We show that the proposed method reduces the size of the operands by half and does not require additional restrictions on the divisor as in the division algorithm in RNS based on the approximate method.

Multiple Error Correction in Redundant Residue Number Systems: A Modified Modular Projection Method with Maximum Likelihood Decoding

Error detection and correction codes based on redundant residue number systems are powerful tools to control and correct arithmetic processing and data transmission errors. Decoding the magnitude and location of a multiple error is a complex computational problem: it requires verifying a huge number of different possible combinations of erroneous residual digit positions in the error localization stage. This paper proposes a modified correcting method based on calculating the approximate weighted characteristics of modular projections. The new procedure for correcting errors and restoring numbers in a weighted number system involves the Chinese Remainder Theorem with fractions. This approach calculates the rank of each modular projection efficiently. The ranks are used to calculate the Hamming distances. The new method speeds up the procedure for correcting multiple errors and restoring numbers in weighted form by an average of 18% compared to state-of-the-art analogs.

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

Medical imaging using different modalities has many problems. The main ones are low informativeness, various distortion noises, and a large amount of information. Fusion, denoising, and visual data compression are used to solve them in practice. Discrete wavelet transform is one way to implement various fusion, denoising, and compression methods for 2D and 3D medical image processing. Medical imaging systems produce increasingly accurate images with scanning technology and digital devices development. These images have improved quality using both higher spatial resolutions and color bit-depth. Processing a large volume of medical imaging data requires considerable resources and processing time. Modern wavelet-based devices for medical image processing do not meet the current performance demand. Hardware accelerators are being designed to solve this problem. This paper proposes new (field-programmable gate array) FPGA accelerators using wavelet processing (WP) with scaled filter coefficients (SFC) and parallel computing in residue number system (RNS) to improve the performance of high-quality 3D medical image WP systems. The computational complexity is reduced using the developed WP method with SFC and the proposed wavelet filter coefficients scaling algorithm. Parallel computing is organized in RNS using moduli sets of a particular type. Hardware implementation of 3D medical image WP using the proposed FPGA accelerators increases device performance by 2.89-3.59 times, increasing the hardware resources by 1.18-3.29 times compared to state-of-the-art solutions. The device performance improvement is achieved while maintaining high-quality 3D medical image processing in peak signal-to-noise ratio terms.

Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation

In the past decades, the Residue Number System (RNS) has been adopted in DSP as an alternative to the traditional two’s complement number system (TCS) because of the savings in area and power dissipation. In this work, we first perform a comprehensive Design Space Exploration (DSE) to analyze the impact of state-of-the-art design tools and libraries on the implementation of the basic operations (i.e., addition and multiplication) used in DSP. From this DSE, we extract the characteristics of the stand-alone RNS and TCS operators in the different design corners, independently of the specific context of the application. Then, we propose a design methodology, based on the DSE, to fully automate the design of digital filters, hiding the detail of the RNS to the designer, and providing optimal power efficient implementations. Our methodology can enable the efficiency in computation (speed and power) in DSP and in emerging applications, such as Machine Learning and Internet-of-Things.

Methods of crypto-stable symmetric encryption in the residual number system

This paper proposes new symmetric cryptography algorithms of Residue Number System and its Modified Perfect Form. According to the first method, ciphertext is regarded as a set of residues to the corresponding sets of modules (keys) and decryption or decimal number recovery from its residues takes place according to the Chinese Remainder Theorem. To simplify the calculations, it is proposed to use a Modified Perfect Form of Residue Number System, which leads to a decrease in the number of arithmetic operations (in particular, finding the inverse and multiplying by it) during the decryption process.Another method of symmetric encryption based on the Chinese Remainder Theorem can be applied when fast decryption is required. In this algorithm, the plaintext block is divided into sub-blocks that are smaller than the corresponding module and serve as remainders on dividing some number, which is a ciphertext, by these modules. Plaintext recovery is based on finding the ciphertext remainders to the corresponding modules. Examples of cryptography algorithms implementation and their encryption schemes are given.The security of the proposed methods is estimated on the basis of the Prime number theorem and the Euler function. It is investigated which bitness and a number of modules are required for the developed symmetric security systems to ensure the same security level as the largest length key of the AES algorithm does. It is found that as the number of modules increases, their bitness decreases. Graphical dependencies of cryptanalysis complexity on bitness and a number of modules are built. It is shown that with the increase of specified parameters, the security of the developed methods also increases.

Метод аппаратной реализации сверточной нейронной сети на основе системы остаточных классов

Convolutional Neural Networks (CNN) show high accuracy in pattern recognition solving problem but have high computational complexity, which leads to slow data processing. To increase the speed of CNN, we propose a hardware implementation method with calculations in the residue number system with moduli of a special type and . A hardware simulation of the proposed method on Field-Programmable Gate Array for LeNet-5 CNN is trained with the MNIST, FMNIST, and CIFAR-10 image databases. It has shown that the proposed approach can increase the clock frequency and performance of the device by 11%-12%, compared with the traditional approach based on the positional number system.

Модификация алгоритма обнаружения и локализации ошибки в системе остаточных классов

This article presents the design of the modified error detection and localization algorithm in the Residue Number System (RNS). Classical redundant RNS with one control modulus can detect one error but not localize it. Two control moduli are used to localize a single error. Presented algorithm can achieve an error correction with a single control modulus transmitted over a reliable communication channel. The proposed approach was verified using Verilog on ASIC in RTL and physical synthesis tool Cadence Genus Synthesis Solution. It significantly reduces the area of the hardware implementation increasing the packing density and more efficient use of silicon resource. It slightly increases the running time compared with the classical algorithm. Distributed data storage was developed to study efficiency of the proposed algorithm.

Evaluation of the reverse transformation methods complexity of the residual number system for secure data storage

The methods of conversion from the residual number system to the decimal number system based on the classical Chinese remainder theorem (CRT) and its improvements CRT I, CRT II are considered in this paper. Analytical dependences of the time complexity of the specified methods are analyzed and constructed. As the result of carried out investigation, it is established that CRT II is characterized by greater efficiency compared to the other methods mentioned above. Examples of the implementation of direct and reverse conversion of RNS based on the application of CRT , CRT I, CRT II are given.

Optimization of Homomorphic Comparison Algorithm on RNS-CKKS Scheme

The sign function can be adopted to implement the comparison operation, max function, and rectified linear unit (ReLU) function in the Cheon&#x2013;Kim&#x2013;Kim&#x2013;Song (CKKS) scheme; hence, several studies have been conducted to efficiently evaluate the sign function in the CKKS scheme. Recently, Lee <i>et al.</i> (IEEE Trans. Depend. Sec. Comp.) proposed a practically optimal approximation method for the sign function in the CKKS scheme using a composition of minimax approximate polynomials. In addition, Lee <i>et al.</i> proposed a polynomial-time algorithm that finds the degrees of component polynomials that minimize the number of non-scalar multiplications. However, homomorphic comparison/max/ReLU functions using Lee <i>et al.</i>&#x2019;s approximation method have not been successfully implemented in the residue number system variant CKKS (RNS-CKKS) scheme. In addition, the degrees of component polynomials found by Lee <i>et al.</i>&#x2019;s algorithm are not optimized for the RNS-CKKS scheme because the algorithm does not consider that the running time of non-scalar multiplication depends significantly on the ciphertext level in the RNS-CKKS scheme. In this study, we propose a fast algorithm for the inverse minimax approximation error, which is a subroutine required to find the optimal set of degrees of component polynomials. The proposed algorithm facilitates determining the optimal set of degrees of component polynomials with higher degrees than in the previous study. In addition, we propose a method to find the degrees of component polynomials optimized for the RNS-CKKS scheme using the proposed algorithm for the inverse minimax approximation error. We successfully implement the homomorphic comparison, max function, and ReLU function algorithms on the RNS-CKKS scheme with a low comparison failure rate (<inline-formula> <tex-math notation="LaTeX">$&lt; 2^{-15}$ </tex-math></inline-formula>), and provide various parameter sets according to the precision parameter <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>. We reduce the depth consumption of the homomorphic comparison, max function, and ReLU function algorithms by one depth for several values of <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>. In addition, the numerical analysis demonstrates that the homomorphic comparison, max function, and ReLU function algorithms using the degrees of component polynomials found by the proposed algorithm reduce the running time by 6&#x0025;, 7&#x0025;, and 6&#x0025; on average, respectively, compared with those using the degrees of component polynomials found by Lee <i>et al.</i>&#x2019;s algorithm.

Efficiency of transmission of discrete messages in a residue number system

The authors analyze the process of transmission of discrete messages in a residue number system, i.e., the efficiency of the representation of decimal numbers in a residue number system for different values ​​of the module, that is. It is noted that it is characteristic of modern information transmission systems that the information is contained in the information parameter at a fixed interval of the Nyquist element. The increase in the capacity is achieved by increasing the number of states of the information parameter in this interval, i.e., the number of different amplitudes, phases and frequencies of the carrier oscillation. In addition, using a residue number system when representing decimal numbers, the sum of the digits of individual numbers in most cases is less than 10 (except for the number N104) and an increase in the probability of not using moduli Е 3; 5; 7 leads to an increase in the entropy of the corresponding events.

En-AR-PRNS: Entropy-Based Reliability for Configurable and Scalable Distributed Storage Systems

Storage-as-a-service offers cost savings, convenience, mobility, scalability, redundant locations with a backup solution, on-demand with just-in-time capacity, syncing and updating, etc. While this type of cloud service has opened many opportunities, there are important considerations. When one uses a cloud provider, their data are no longer on their controllable local storage. Thus, there are the risks of compromised confidentiality and integrity, lack of availability, and technical failures that are difficult to predict in advance. The contribution of this paper can be summarized as follows: (1) We propose a novel mechanism, En-AR-PRNS, for improving reliability in the configurable, scalable, reliable, and secure distribution of data storage that can be incorporated along with storage-as-a-service applications. (2) We introduce a new error correction method based on the entropy (En) paradigm to correct hardware and software malfunctions, integrity violation, malicious intrusions, unexpected and unauthorized data modifications, etc., applying a polynomial residue number system (PRNS). (3) We use the concept of an approximation of the rank (AR) of a polynomial to reduce the computational complexity of the decoding. En-AR-PRNS combines a secret sharing scheme and error correction codes with an improved multiple failure detection/recovery mechanism. (4) We provide a theoretical analysis supporting the dynamic storage configuration to deal with varied user preferences and storage properties to ensure high-quality solutions in a non-stationary environment. (5) We discuss approaches to efficiently exploit parallel processing for security and reliability optimization. (6) We demonstrate that the reliability of En-AR-PRNS is up to 6.2 times higher than that of the classic PRNS.

Zero-Aware Low-Precision RNS Scaling Scheme

Scaling is one of the complex operations in the Residue Number System (RNS). This operation is necessary for RNS-based implementations of deep neural networks (DNNs) to prevent overflow. However, the state-of-the-art RNS scalers for special moduli sets consider the 2k modulo as the scaling factor, which results in a high-precision output with a high area and delay. Therefore, low-precision scaling based on multi-moduli scaling factors should be used to improve performance. However, low-precision scaling for numbers less than the scale factor results in zero output, which makes the subsequent operation result faulty. This paper first presents the formulation and hardware architecture of low-precision RNS scaling for four-moduli sets using new Chinese remainder theorem 2 (New CRT-II) based on a two-moduli scaling factor. Next, the low-precision scaler circuits are reused to achieve a high-precision scaler with the minimum overhead. Therefore, the proposed scaler can detect the zero output after low-precision scaling and then transform low-precision scaled residues to high precision to prevent zero output when the input number is not zero.