Reset Pin Research Articles

Using Universal Nand-nor-inverter Gate to Design D-latch and D Flip-flop in Quantum-dot Cellular Automata Nanotechnology

The process of reducing dimensions in CMOS technology and also making digital devices more portable, faces serious challenges such as increasing frequency and reducing power consumption. For this reason, scientists are looking for a solution such as replacing CMOS technology with other technologies including Quantum-dot Cellular Automata (QCA) technology and many researches have designed digital circuits by using QCA technology. Flip-flops are one of the main blocks in most digital circuits. In this paper, a D-type flip-flop (D-FF) is presented in QCA technology that a majority gate has been used in its feedback path to reset. The D-FF is designed by the proposed D Latch which is based on Nand-Nor-Inverter (NNI) and a new inverter gate that the proposed D latch has 24 cells and 0.5 clock cycle latency and 0.02 〖μm〗^2 area. The new inverter gate of the D-FF has output signal with high polarization level and lower area than previous inverters and the NNI gate of the D-FF is a universal gate. One of the applications of D-FFs with reset pin is the use in Phase-frequency detector (PFD). In the proposed scheme, a reset feature has been added to D-FF since the PFD structure can be designed. All of the proposed schemes are evaluated by the QCADesigner software and energy consumption simulations are estimated using QCAPro software for all proposed circuits.

Designing Bi-directional Counters Using Quantum-dot Cellular Automata Nanotechnology

One of the major problems in designing highly compact integrated circuits is the power consumption of the circuits. Therefore, several technologies have been introduced to overcome the problems facing MOSFET technology. One of these technologies is the Quantum-Dot Cellular Atomata (QCA), which has several advantages. In this paper, we focus on computational logic gates based on the T-Latch circuit. T-latch is the basis of many circuit in arithmetic logic unit (ALU). The proposed structure for T-latch has a lower number of cells, occupied area and lower power consumption than existing methods. In the proposed T-Latch, compared to previous best designs, 6.45% cross section area and 44.49% power consumption were reduced. Also in this paper, for the first time a T-latch with reset terminal and a T-Latch with both set and reset terminals were designed. In addition, using the proposed T-latch, a 3-bit bidirectional up-down counter which consists of 204 quantum cells, 0.26 µm2 cross-sectional area, delay of 5.25 clock cycles, a three-bit up-down counter with a reset pin and a three-bit up-down counter with set and reset terminals were made. The proposed up-down circuits are designed for the first time in QCA technology. All the design and simulation results are done in QCADesigner software.

4-Bit serial shift register with reset ability and 4-bit LFSR in QCA technology using minimum number of cells and delay

Quantum-dot cellular automata (QCA) nanotechnology is one of the proposed technologies for replacing CMOS technology. Shift registers are one of the important areas in the design of digital circuits and memory structures. Given the importance of shift registers, in this paper, new structures have been proposed for shift registers in QCA nanotechnology. At first, proposed D-latch is presented to be used in the main block of shift registers, which has only 18 cells, a delay of 0.5 cycles and less area than previous designs. Subsequently, a 4-bit series register will be presented using the proposed D-latch, which is at least 30% lower than the previous ones in terms of cell numbers and area. In addition, a reset pin is needed in shift registers which are used in microprocessors. Most of the previous designs did not have the reset pins and therefore a new version of 4-bit shift register which has the reset pin will be presented in this paper. New and former designs have been expanded from 2 bits to 8 bits, and parameters variations are presented in the table and diagrams. The proposed new designs have interesting features in terms of stability, number of cells and occupied area, compared to previous designs that do not have the reset capability. In addition, the proposed shift register is used to design an optimized LFSR circuit in QCA nanotechnology with only 157 cells and 0.2 µm2 area.

Design of Multiplexer-Based D Flip-Flop with Set and Reset Ability in Quantum Dot Cellular Automata Nanotechnology

Despite many advances in the electronics industry, much effort is being made to improve existing technologies. One of the proposed technologies in this field is the Quantum Cellular Automata (QCA), which provides low power, low area, high density, and high-speed structures. Latches and flip-flops are always the most commonly used circuits in digital design, and designing these structures with greater stability and capability is very important. In this paper, with the use of the appropriate D latch in terms of volume and delay, the edge sensitive D flip-flops in the QCA technology are introduced with the ability of set and reset based on optimized multiplexer design. The simulation results show that the proposed designs are stable and useful structures in terms of area, delay and complexity and are suitable for use in the larger circuits. For example proposed synchronous rising edge D flip-flop with set and reset pins has 74 quantum cells, 2.5 clock cycles delay and 0.09μm2 occupied area.

Novel D Latches and D Flip-Flops with Set and Reset Ability in QCA Nanotechnology Using Minimum Cells and Area

Emerging nanotechnology of Quantum-dot Cellular Automata (QCA) is one of the alternative technologies for CMOS technology. One of the essential parts of the structure of each arithmetic and logic units on the processors is the circuits that are affiliated with the Flip-Flops. Therefore, considering the importance of D Flip-Flops among different types of Flip-Flops and their more efficient performance, this paper presents new structures for D Latch and D Flip-Flops in QCA nanotechnology. First, the proposed D latch in QCA technology which has only 19 cells and a delay of 0.75 cycles is reported and will be compared with previous works. The comparison shows that the proposed D latch has the fewer number of cells, smaller area, and less delay. Then there are some methods for converting proposed latch into Flip-Flops, and with the help of these, new proposed falling edge, rising edge and dual edge triggered D Flip-Flops are suggested. The proposed structures have been designed in one layer. In terms of occupied area, delay and number of cells, the proposed D Flip-Flops are superior to previous structures. At last, set and reset pins will be added to proposed designs, and this is another advantage of proposed circuits, which is rarely seen in previous structures.

Immunity Test of a Microcontroller by Using Transmission Line Pulse Generator

Electrostatic discharge is a familiar interfere. Repeatability of discharge current is poor. Transmission line pulse (TLP) is used in study of immunity of a microcontroller. A TLP generator is first manufactured with the rise time of output pulse less than 1ns. Then couplings by electric field probe, magnetic field probe and direct injection are presented. And immunity test of a microcontroller is done by using the TLP generator and probes. Results show that the tested microcontroller is more sensitive to magnetic field interference; reset pin and crystal oscillator pin of the chip are more sensitive than other pins under action of direct injection interference.

Swift Self-Starting Design of Sequential Logic Circuit Based on Karnaugh Map

To make the circuit self-start swiftly in the environment with much disturbance, according to the principle of being propitious to simplify state equation and output equation, assigned a next state for each bound term on Karnaugh map, and the next state must be a state of the valid cycle, at last tested the method by simulation. In the simulation, imitated the disturbance by the set pin or reset pin of flip-flop. The simulation based on electronics workbench 5.0C shows the effectiveness and feasibility of the method.