Reset Circuit Research Articles

A Scalable Delay‐Expanding Technique for Low‐Area On‐Chip Power‐On Reset Circuits

ABSTRACTA scalable structure is presented and analyzed that can provide delays in a wide range (microseconds to minutes) for the power‐on reset circuit. The proposed structure enables the implementation of these delays entirely on‐chip through the utilization of a provisional oscillator and a set of flip‐flops. The optimal number of flip‐flops can be determined through an area optimization process. The proposed power‐on reset circuit thresholds demonstrate the process, voltage, temperature (PVT) tolerance, facilitated by the use of resistors of the same type. Notably, the thresholds and provided delay for this circuit are supply‐rise‐time independent. The structure has been implemented in a 0.18‐μm CMOS technology, occupying an active area of 48 × 40 μm2.

High-speed Ta2O5-based threshold switching memristor for LIF neurons

Due to their high similarity to biological ion channels, low power consumption, small footprint, and the fact that they do not require reset circuits, threshold switching memristors have been intensively studied for simulating neurons in neuromorphic chips. Switching speed is one of the key challenges which limit the application of threshold switching memristors in chips. In this study, Ta2O5 threshold switching memristors with high switching speeds were prepared by doping with silver. The results show that 14 wt. % Ag doped Ta2O5 threshold switching memristors exhibit excellent bi-directional threshold switching performance, featuring fast switching speeds (<20 ns, <18 ns), low leakage currents (<10 pA), and high switching ratio (>107). According to the field nucleation theory, the rapid switching speed can be attributed to the low nucleation energy (0.26 eV) of silver within the Ta2O5 matrix, which is achieved by incorporating 14 wt. % Ag during the doping process. Based on Pspice, a LIF (leaky integrate-and-fire) neuron based on the silver nanoparticles doped Ta2O5 threshold switching memristors is built, and its firing function has been simulated. The results show that the LIF neuron with a short switching time is able to excite pulse spiking with high frequencies. These results demonstrated that the silver nanoparticles doped Ta2O5-based threshold switching memristors hold significant potential for constructing high-speed artificial neural networks.

All-Ferroelectric Spiking Neural Networks via Morphotropic Phase Boundary Neurons.

Artificial neurons and synapses are crucial for efficiently implementing spiking neural networks (SNNs) in hardware. The distinct functional requirements of artificial neurons and synapses present significant challenges in the implementation of area- and energy-efficient SNNs. This study reports an all-ferroelectric SNN system through co-optimization of material properties and device configurations using wafer-scale atomic layer deposition. For the first time, a double-gate (DG) morphotropic phase boundary-based thin-film transistor (MPBTFT) is utilized for a leaky integrate-and-fire (LIF) neuron. The DG MPBTFT-based LIF neuron eliminates the need for capacitors and reset circuits, thereby enhancing area and energy efficiency. The DG configuration demonstrates various neuronal functions with high reliability. Co-optimizing materials and devices significantly enhance the performance and functional versatility of artificial neurons and synapses. Meticulous material engineering facilitates the seamless co-integration of DG MPBTFT-based neurons, ferroelectric thin-film transistor (TFT)-based synapses, and normal TFTs on a single wafer. All-ferroelectric SNN systems achieved a high classification accuracy of 94.9%, thereby highlighting the potential of DG MPBTFT-based LIF neurons for advanced neuromorphic computing.

Research on Internet of Things based Hand-Pushed Wheel Rangefinder Technology

In order to address the accuracy issues of the hand-pushed wheel rangefinder, this paper proposes a solution that integrates IoT technology and angle sensors into the device to enhance accuracy and informationization level. A wheel rangefinder based on Internet of Things (IoT) technology is designed. The central control device of this system adopts a STM32 microcontroller. The system includes a voltage boosting and dropping circuit, a reset circuit, a gyroscope module, an indicator light module, and a Wireless Fidelity (WiFi) transmission module. The gyroscope module is designed to calculate the actual running distance of the handcart through angle measurement, enabling real-time recording and remote transmission of measurement data. Compared with total stations, rangefinders, and measuring ropes, this system is of good effectiveness and its average error is within 1%. At the same time, it has the capability to save measurement information to the database.

Design and Application of Indoor Intelligent Light Emitting Diode Lighting

In this research, an indoor intelligent light emitting diode (LED) lighting device is designed, which includes environmental brightness detection module, temperature detection module, display module and LED driving module. S5052 photodiode is selected for environmental brightness level, which can work normally in the environment of −25 °C to 75 °C, and the analog signal is converted into recognizable digital signal through MCP3204 A/D converter. The DS18B20 sensor is selected to measure the temperature, which is connected with the single chip microcomputer to collect the indoor temperature signal. Adopting constant current drive mode, HV9910 LED driver chip is selected to convert 220 V AC power supply into 5 V DC power supply, and AD1585 chip is used as reference power supply to suppress the fluctuation of DC power supply. The display module takes STC12C5A60S2 single chip microcomputer as the control module, and integrates MAX810 special reset circuit, 2-channel PWM and 8-channel 10-bit A/D converter, thus simplifying the peripheral circuit. During the test, the single chip microcomputer is initialized, the intelligent control part is embedded with data analysis technology, and the modular debugging method is adopted, and the illumination brightness value meets the expectations under different conditions. The ambient temperature is compared with the test temperature to keep consistent. Based on PWM method, dimming is carried out, and two environments are set (the first one is to maintain the ambient light illumination of 300lx, and the other one is to maintain the ambient light illumination of 100lx). The results show that the designed system is suitable for different lighting environments and can adjust the indoor lighting brightness adaptively.

Hardware Implementation of a Fully Functional Stochastic p‐STT Neuron for Probabilistic Computing

AbstractA stochastic binary neuron is developed for probabilistic computing using a perpendicular spin‐transfer torque (p‐STT) neuron device and its associated peripheral circuits. The p‐STT neuron device, featuring a 300‐nm‐diameter pillar structure and a perpendicular magnetic‐tunnelling‐junction spin valve, is fabricated to exhibit stochastic switching behavior characterized by a sigmoidal function. The stochastic switching mechanism is influenced by the presence of defect sites within the device. The hardware implementation encompasses the construction of the neuron peripheral circuit, including the fire‐spike generation, sensing amplifier, and reset circuit, using a 28‐nm‐design‐rule complementary metal‐oxide‐semiconductor (C‐MOSFET) process. This hardware realization also demonstrates stochastic switching behavior with a sigmoidal function. However, a slight shift toward higher input voltage spike amplitudes is observed compared to the p‐STT neuron device alone, owing to voltage drop within the peripheral circuit. Furthermore, the software‐based investigation focuses on validating the feasibility of a spiking neural network. The temporal correlation detection is estimated using the stochastic switching probability derived from the hardware implementation, indicating successful synchronization between the correlated input neuron and the output p‐STT neuron.

An ultra-low quiescent current power-on reset circuit with DDPG method

An ultra-low quiescent current power-on reset (POR) circuit with double-delay pulse generation (DDPG) method is presented in this paper. The circuit is designed for non-volatile memory (NVM) systems, aiming to ensure reliable initialization and enhance overall efficiency. To address the challenge of inaccurate trigger-point voltage caused by process, voltage, temperature (PVT) and ramp time variations, a novel pulse generation method is proposed. Additionally, the circuit further improves the reliability of pulse duration through the utilization of low-cost current reference generators. Implemented in standard 40 nm CMOS technology, the delay-based POR circuit consumes only 0.24 nA quiescent current and occupies a compact area of 25.6μm×102μm. The simulation results demonstrate a typical pulse duration time of 28μs, with a temperature coefficient (TC) of 101.4 ppm/°C. The high reliability and low overhead of this circuit make it suitable for NVM systems and other fast power-on applications.

Design of New LED Curtain Wall Controller and Its Effect in Architectural Decoration

In recent years, LED with high brightness or ultra-high brightness has appeared. Because of its low production cost, it has been widely used. Compared with other display media, LED has the advantages of rich display content, wide dynamic range, vivid picture, no pollution, long life, etc., so it is used in building curtain wall facade decoration. This research designs LED curtain wall control system, the use of SD600 chip dimming control of LED, the use of absorbing current mode LED drive, further design of single SD600 chip application circuit, multi-SD600 chip application circuit. LED curtain wall display text need to design the corresponding graphic processing hardware, the hardware is composed of ARM microprocessor LPC2210 and its related peripheral circuits. The core chip of the LPC2210 processor chip needs 1.8 V working voltage, and the I/O interface voltage is 3.3 V, so it is necessary to design the corresponding power circuit; The system clock is adjusted through the internal PLL circuit to make the system run faster and design its crystal oscillator circuit; The power monitoring chip CAT1025JI-30 is adopted to build reset circuit, 20-pin interface type JTAG interface circuit; It is considered that the UARTO interface can’t be directly connected with the RS232 interface of PC, the MAX3232 chip is introduced for level conversion, and the serial interface circuit based on LPC2210 is designed. In the experiment, the new technology is used for outdoor lighting LED curtain wall construction, and the development tool uses the ADS1.2 provided by ARM company. The μC/OS-II embedded operating system is introduced to control the graphic processing hardware resources, reading the file from the SD card, and writing the text file and BMP file into the three-dimensional array, the corresponding text and pattern effect are displayed in the LED curtain wall.

RRAM-Based Energy Efficient Scalable Integrate and Fire Neuron With Built-In Reset Circuit

In this brief, we propose a Resistive Random Access Memory (RRAM) based self-resetting Integrate and Fire ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}\&amp;\text{F}$ </tex-math></inline-formula> ) neuron. The proposed neuron circuit does not require any external bias voltage and the integration of control unit required to reset RRAM into neuron circuit optimizes its overall power consumption. The neuron circuit proposed in this brief consists of two RRAMs for integrate and fire operations, whereas, pulse propogation and reset circuit consists of 22 CMOS transistors. It consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5~fJ$ </tex-math></inline-formula> per spike, which is 48% and 53% less than the recent neurons designed using, nanoscale FBFET and PDSOI-MOSFET, respectively. The operating frequency of proposed neuron ranges from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$277~KHz$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$03~MHz$ </tex-math></inline-formula> , which is at least 7.5% and 10% higher than the operating frequencies of above mentioned recent neurons, respectively. The inclusion of reset circuit into RRAM based neuron circuit enables the implementation of large scale spiking neural network (SNN), which makes it superior in terms of power and energy consumption.

Automated, adaptive, fast reset circuit for wide-energy range detector front-end

In this article, we present a front-end amplifier that is equipped with a precise, fast, and automated reset circuit responsible for two actions: restoring the charge-sensitive amplifier output voltage from a pulse level to baseline, and the analog-to-digital conversion of the pulse amplitude. Importantly, the circuit is self-clocking, which allows to take advantage of the modern submicrometer CMOS process, and thus speed-up the reset and conversion phases. Thanks to the proposed approach, the fast clock signal distribution and an independent analog-to-digital converter per channel are not required, saving both the power consumption and the silicon area. The presented circuitry was adopted into 100-pixel-shaped recording channels and sent for fabrication in the CMOS 28 nm process.

Wireless sensor network node real-time positioning system based on embedded MCU

In order to reduce the node positioning error and improve the stability of the system, this paper proposes and designs a new wireless sensor network node real-time positioning system based on Embedded MCU. Firstly, the characteristics of wireless sensor networks are analyzed. Secondly, in the hardware part of the system, the embedded node positioning MCU, reset circuit, debugging circuit and serial port circuit are designed to meet the node positioning requirements of the system. Finally, in the software design part, the least square algorithm is used to construct the real-time positioning function of wireless sensor network nodes, and the bat algorithm is used to solve the objective function to complete the real-time positioning of nodes. The experimental results show that all functions of the designed system operate normally, and the average error of node positioning is only 0.21.

Circuit Design of Counting Electronic Scale Based on STC89C51 Single Chip Microcomputer

The main purpose of electronic scales is to measure, which can also be said to be for trading. Electronic scales have their relevant numerical measurement value restrictions when they are used. Therefore, they can only be used effectively within the measurement value range when they are used. As long as the weight does not exceed the measurement limit, they can be used at will. This measurement method greatly improves the measurement speed and the user's trading speed. STC89C51 single chip microcomputer as an 8-bit single chip microcomputer, first of all, the price is relatively low. The number of pins of 51 single chip microcomputer is up to 40. After subtracting some power supplies and special pins, 32 pins can be used, and all 32 pins can be used as input and output pins. Therefore, the performance price ratio of 51 single chip microcomputer is relatively high. At the same time, the application circuit of 51 single chip microcomputer is relatively simple, and only the crystal oscillator circuit and reset circuit are needed to achieve work. Besides, 51 single chip microcomputer also has serial communication, timer, external interrupt and other on-chip resources, which can meet the special requirements of some systems. Finally, in terms of programming, the 51 single-chip microcomputer can be used only after loading the header file, without configuring the input and output ports, and is also very convenient in programming. Therefore, STC89C51 single chip microcomputer is used as the basis and Proteus and KILL software are used to realize the design of electronic scales.

Compact artificial neuron based on anti-ferroelectric transistor

Neuromorphic machines are intriguing for building energy-efficient intelligent systems, where spiking neurons are pivotal components. Recently, memristive neurons with promising bio-plausibility have been developed, but with limited reliability, bulky capacitors or additional reset circuits. Here, we propose an anti-ferroelectric field-effect transistor neuron based on the inherent polarization and depolarization of Hf0.2Zr0.8O2 anti-ferroelectric film to meet these challenges. The intrinsic accumulated polarization/spontaneous depolarization of Hf0.2Zr0.8O2 films implements the integration/leaky behavior of neurons, avoiding external capacitors and reset circuits. Moreover, the anti-ferroelectric neuron exhibits low energy consumption (37 fJ/spike), high endurance (>1012), high uniformity and high stability. We further construct a two-layer fully ferroelectric spiking neural networks that combines anti-ferroelectric neurons and ferroelectric synapses, achieving 96.8% recognition accuracy on the Modified National Institute of Standards and Technology dataset. This work opens the way to emulate neurons with anti-ferroelectric materials and provides a promising approach to building high-efficient neuromorphic hardware.

An Artificial Neuron with a Leaky Fin‐Shaped Field‐Effect Transistor for a Highly Scalable Capacitive Neural Network

A capacitive neural network with a capacitive crossbar array that can replace a traditional resistive crossbar array can drastically lower static power consumption during reading operations because a capacitor consumes only dynamic power. Herein, a leaky fin‐shaped field‐effect transistor (L‐FinFET) neuron is fabricated and then applied for use in a highly scalable capacitive neural network with leaky integrate‐and‐fire (LIF) operations that are attributed to a leaky charge trap layer in a gate stack. An additional circuit such as a voltage‐to‐current converter (V–I converter) is no longer required when the L‐FinFET is applied to the capacitive neural network, as the L‐FinFET can directly accept a voltage signal from capacitive synapses. Furthermore, a reset circuit is not necessary given the ability to spontaneously restore to the initial state owing to the leaky charge trap layer. A highly scalable capacitive neural network is realizable due to the size‐reduction ability of the L‐FinFET and the simplified circuit. Finally, an entirely hardware‐based capacitive neural network with the L‐FinFET is demonstrated for the recognition of a simple pattern.

(Digital Presentation) Electrochemical Metallization Cell Based Memristive Neuron Chip Fabricated with 28nm CMOS Process for Real-Time Unsupervised Learning and Pattern Recognition

Spiking neurons communicate with other neurons using sparse and binary signals in a human brain, so they can achieve real-time processing of the information with ultra-low power consumption[1,2]. Thereby, spiking neurons are essential elements for building an energy-efficient biomimetic spatiotemporal system. Recently, to emulate the behavior of biological neuron, many researches for memristive device-based neurons with peripheral circuits (i.e., sense-amplifier or reset circuit)[3] and complementary metal-oxide-semiconductor (CMOS) neurons with capacitors have been reported[4]. Most of the reported memristive device-based neurons required a high operation voltage (>1.2 V) for emulating integrate function of a biological neuron. In addition, complementary metal-oxide-semiconductor-based neurons could not achieve high neuronal density due to using a capacitor in emulating integrate function.In this study, therefore, we propose an electrochemical metallization cell based memristive neuron chip fabricated with 28-nm CMOS process having a low operation voltage (<0.7 V) for emulating integrate function. In addition, since the proposed electrochemical metallization cell based memristive neuron chip does not require a capacitor for emulating integrate function, it can realize a high neuronal density. The memristive neuron chip exhibited a typical integrate-and-fire function; particularly, the frequency of generating a spiking output signal exponentially increased with the input voltage amplitude. Moreover, a spiking neural network was designed using the memristive neuron chip and the software program consisting of a crossbar synaptic memristor array, simplified spike-timing-dependent-plasticity learning rule, and current-to-voltage converters. Using the co-designed spiking neural network with software and hardware, real-time unsupervised learning was realized. Finally, using the trained spiking neural network, a real-time classification for the MNIST hand-written image taken by a live webcam was successfully performed in an inference process. Acknowledgement This research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT(2021M3F3A2A01037733). Reference Mead, C. Neuromorphic Electronic Systems. Encycl. Comput. Neurosci. 78, 1979–1979 (2015).Douglas, R. Neuromorphic Analogue VLSI. Annu. Rev. Neurosci. 18, 255–281 (1995).Tuma, T., Pantazi, A., Le Gallo, M., Sebastian, A. & Eleftheriou, E. Stochastic phase-change neurons. Nat. Nanotechnol. 11, 693–699 (2016).Aamir, S. A., Müller, P., Hartel, A., Schemmel, J. & Meier, K. A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic system. Eur. Solid-State Circuits Conf. 2016-Octob, 71–74 (2016). Figure 1

P‐16.8: The Vth shift of ASG after high temperature operating

LCD with ASG inside may encounter malfunction phenomenon after high temperature reliability analysis (RA). The main reason we found is the Vth shift. We reported the characterization method of how to design the ASG with wide operating temperature in the former article [1]. In order to quantify the Vth deterioration, we designed a 3.45inch panel with circular active area and ASG driven units. Among the ASG units, one of the ASG unit was designed that can test TFT Id-Vg. The test pads were designed on the CFOG side. We tested the Id-Vg curves of each TFT before and after 85°C high temperature operation reliability analysis. We analyzed the Vth shift of each TFT and discussed the result. The mechanization of the reset circuit deterioration and the solutions to achieving high temperature reliability test are summed in the discussion.

Active and Passive Reset Circuits for Multistage Magnetic Pulse Compression (MPC) Circuits Used in Gas Laser Applications

Magnetic pulse compression (MPC) circuits are commonly used in pulsed power circuits for powering gas lasers to shorten the duration of the pulse. If the core of every magnetic switch in the MPC is biased to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-\Delta B_{r}$ </tex-math></inline-formula> by a reset circuit, then the voltage hold-off time is doubled, and the cross-sectional area required is halved. Reset circuits must be isolated from the high-voltage pulses appearing in the pulsed power circuit using filters. The required filter (inductor) size becomes too large if the reset circuit is connected directly in parallel to the magnetic switches, especially if the volt-sec product across the filter inductor is large. The most common, existing reset circuits available in the literature directly connect in parallel to the magnetic switch ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$s$ </tex-math></inline-formula> ) and, therefore, require larger filter sizes to protect the reset circuitry. In addition, reset circuits cannot always be wound on the magnetic core to create a step-down transformation of the pulsed power voltages (lack of physical space or the use of a single primary winding). This article proposes a new reset circuit topology which resolves these problems by enabling the use of the smallest possible filter size (inductance value). In addition, only a single reset circuit is needed to reset multiple magnetic switches in the MPC network. An active reset circuit is also proposed which is more suitable for resetting magnetic cores that are relatively harder, i.e., requiring higher H values to saturate (equivalent currents greater than a few amperes). The reset circuits discussed in this article can in general be applied to many pulsed power applications employing MPC networks.

An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology

In this brief, an accurate low-power power-on-reset circuit is proposed. In order to get an accurate trip-voltage with little overhead, a low-power architecture based on current reference and current comparator is proposed. The reference current in the proposed power-on-reset circuit is mainly provided by the sub-threshold current of several native NMOS transistors, and a stable hysteresis window can be obtained by adjusting the number of enabled native NMOS transistors. Measurement results based on 55nm CMOS process show that the proposed power-on-reset circuit consumes only 32nW at the supply voltage of 0.5V. The measured power-on-reset trip-voltage is 0.45V with a temperature coefficient of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$227~\mu \text{V}/^{\circ }\text{C}$ </tex-math></inline-formula> . Since the proposed power-on reset circuit consists of only 10 transistors, the area of the proposed power-on-reset circuit is as low as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$67.5~\mu \text{m}^{2}$ </tex-math></inline-formula> .

All digital sliding mode observer of a feedback-free interferometer for high dynamic range detection.

A passive interferometry phase detection method is presented, which emulates the closed-loop high gain approach technique. This method comprises an all-digital closed-loop observer based on the variable structure and sliding modes nonlinear control theory, able to demodulate the phase of an open-loop feedback-free interferometer hardware. A proof-of-concept experiment is conducted by measuring complex displacements (module and angle) generated by a piezoelectric actuator. The results show that this method simplifies the optical hardware while providing features such as direct detection of the optical phase, increase of the dynamic range, high robustness, and dismissing of the feedback phase modulator and reset circuits.

A Review of Artificial Spiking Neuron Devices for Neural Processing and Sensing

AbstractA spiking neural network (SNN) inspired by the structure and principles of the human brain can significantly enhance the energy efficiency of artificial intelligence computing by overcoming the bottlenecks of the conventional von Neumann architecture with its massive parallelism and spike transmissions. The construction of artificial neurons is important for the hardware implementation of an SNN, which generates spike signals when enough synaptic signals are gathered. Because circuit‐level artificial neurons with comparator and reset circuits require considerable hardware area, intensive efforts are devoted in recent years for building artificial neurons at the device level for better area efficiency. Furthermore, artificial sensory neuron devices, which perform neural processing and sensing concurrently, have recently been developed in order to reduce the hardware cost and energy consumption of traditional sensory systems through in‐sensor computing. This review article surveys and benchmarks the recent progress of artificial neuron devices for neural processing and sensing. First, various artificial neuron devices are summarized, including single‐transistor neurons (1T‐neurons), memristor neurons, phase‐change neurons, magnetic neurons, and ferroelectric neurons. Next, cointegration technologies with artificial synaptic devices and artificial sensory neurons for in‐sensor computing are introduced. Finally, the challenges and prospects for developing artificial neuron devices are discussed.