Given the power demands of DSP operations in portable or embedded devices, especially in error-resilient applications such as the multimedia and image processing, approximation strategy is proposed as a viable solution. By deliberately reducing computational precision, various DSP components such as adders, multipliers, and compressors can be designed with lower power requirements. This review explores the optimization of these components at different design levels, including architectural and circuit levels. Specifically, this paper goes deeper into the design of approximate adders, compressors, and multipliers, essentially highlighting their impact on power efficiency and computational accuracy for image/video compression applications. Through analyzing and discussing the different designs, this paper elaborates the trade-offs between power savings and error rates, ultimately demonstrating the potential of approximation techniques in reducing power consumption without significantly compromising performance.
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