Repetitive Avalanche Research Articles

Suppression Effect of Split-Gate Structure on Repetitive Avalanche Stress Induced Degradation for SiC MOSFETs

Suppression Effect of Split-Gate Structure on Repetitive Avalanche Stress Induced Degradation for SiC MOSFETs

Avalanche ruggedness and failure mode of SiC trench MOSFETs

Avalanche ruggedness of SiC MOSFETs is of interest for many researchers since these devices are used in various applications. Existing inductances in the application circuits are the main reason that SiC MOSFETs may enter into avalanche condition. Under certain avalanche operating conditions, the device failure is inevitable. Avalanche failures of SiC MOSFET are usually classified into current-driven and temperature-driven categories. In this paper single-pulse avalanche behaviour of SiC trench MOSFETs of different voltage classes is experimentally investigated. The measurements were performed under various conditions of current, energy, avalanche time and temperature. To gain a better understanding of device failure and to correlate with the experimental results, 1D thermal simulations were carried out and critical chip temperatures which are expected to cause device failures are shown. Furthermore, repetitive avalanche measurements and parameter analyses are discussed. It is shown that SiC trench MOSFETs of different chip sizes show similar avalanche ruggedness. The critical chip temperatures were found to be similar for devices of all avalanche breakdown voltage classes. No drift of the relevant device parameters has been seen after repetitive avalanche measurements. The method used in this work can be used to predict the avalanche behaviour of SiC trench MOSFETs.

Investigation of Failure Mechanisms of 1200 V Rated Trench SiC MOSFETs Under Repetitive Avalanche Stress

In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance caused by thermal fatigue is observed.

Experiment and analysis of repetitive avalanche low-current stress on 4H-SiC power devices

As a kind of 4H-SiC power device, the junction barrier Schottky (JBS) rectifiers, only containing the transition p + implantation region at the edge of the active region in the termination region, are adopted and fabricated to analyze the effect of the repetitive avalanche low-current stress on the SiO2/4H-SiC interfacial state of the devices. The breakdown voltage (BV) of the device shifts after the repetitive avalanche current stress, which results from the electron injects into the SiO2/4H-SiC interface and trapped by the interface states. Meanwhile, there is a tradeoff between the quantities of the trapped and de-trapped electrons by the SiO2/4H-SiC interface states when the BV reaches its saturated value. The junction temperature, total amount of carriers generated in the single avalanche event and repetitive total avalanche energy, affected by the pulse period (T), pulse number and turn-on period (D), are the key factors that affect the level of the BV shift.

Robust Through-Fin Avalanche in Vertical GaN Fin-JFET With Soft Failure Mode

We study the inherent ruggedness of the avalanche through the fin channel, a new avalanche mode in a vertical GaN power Fin-JFET, through single-pulse and repetitive avalanche circuit tests. By turning on the gate during avalanche, the major avalanche current path migrates from the p-GaN gate to the n-GaN fin channel. The single-pulse critical avalanche energy density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {AVA}}$ </tex-math></inline-formula> ) was measured to be 10 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is the highest reported in GaN transistors. The Fin-JFET withstood over 3700 repetitive avalanche pulses at 70% of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {AVA}}$ </tex-math></inline-formula> . It exhibits a failure-to-open-circuit signature in single and repetitive avalanche. This soft failure mode allows the device to retain its full breakdown voltage, which is highly desirable for system robustness. By contrast, the through-gate avalanche in Fin-JFETs and the reported avalanche in Si and SiC transistors all show a destructive, failure-to-short-circuit signature. These results show the viability of soft avalanche failure in power devices, provide key robustness references for GaN devices, and suggest the fundamental superiority of moving the avalanche path away from the major blocking junction.

Application of Two-Phase Immersion Cooling Technique for Performance Improvement of High Power and High Repetition Avalanche Transistorized Subnanosecond Pulse Generators

In this article, we show the feasibility of improving the performance of a high voltage and high repetition avalanche transistor pulse generator by applying a two-phase immersion cooling technique. The forced air cooling, single-phase immersion cooling, and two-phase immersion cooling techniques were applied to a 60-stage subnanosecond pulse generator. The experimental results indicate that the two-phase immersion cooling technique can effectively control the temperature rising of the avalanche transistor and, thus, reduce the time base jitter and voltage amplitude jitter. Five types of dielectric fluid with different boiling temperatures were comparatively studied. The FC-72 was finally adopted for the balanced performance on voltage amplitude and repetition rate. The two-phase immersion cooling technique could reduce the thermal resistance between the case and ambient and increase the maximum power from 330 to 876 mW. With this cooling method, the surface temperature of the transistor can be effectively controlled below 62 °C. The pulse generator could achieve outstanding performance with a voltage of 2350 V and a rise time of 180 ps. It can work stably at 200 kHz for more than 30 min, and the burst repetition rate could be 260 kHz within 1 min. This article offers new perspectives in the design of high repetitive avalanche transistorized subnanosecond generators.

Investigation on the Degradations of Parallel-Connected 4H-SiC MOSFETs Under Repetitive UIS Stresses

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications.

Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example.

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

Observation of photoemission behaviour during avalanche breakdown of insulated gate bipolar transistor with defect in the metal contact

Under unclamped inductive switching (UIS) condition, there is non-uniformity in the intra-chip distribution of avalanche breakdown current in insulated gate bipolar transistors (IGBTs). The “current filaments”, which are concentrations of current caused by the parasitic PNP transistor, move through the chip and are thought to be related to failures. During the avalanche breakdown, the charge bremsstrahlung generates light over a wide wavelength range. We have previously reported that we constructed an observation system using a photomultiplier tube (PMT) and observed the avalanche breakdown photoemission with nanosecond time resolution. In this study, we used the same observation system to observe the photoemission behaviour of the samples in which the metal electrode was partially removed with a FIB (focused ion beam) to create a defective contact area. In the sample with the pseudo-defect, (a) there was an abnormal emission peak that did not correspond to the avalanche current change, (b) the randomness of the behaviour for each single pulse became extremely low, and (c) the pseudo-defect itself did not trap the current filament. These results may explain the tendency of IGBTs to have a higher probability of failure during repetitive avalanche breakdowns if they contain some defects.

Analysis of Floating Limiting Rings Termination Under Repetitive Avalanche Current Stress for 4H-SiC JBS Rectifiers

The reverse breakdown characteristics of 4H-SiC Junction Barrier Schottky (JBS) rectifiers adopting the different floating limiting rings (FLRs) termination structures are experimented and analyzed under the repetitive avalanche current stress. The experimental results indicate that the breakdown voltage (BV) shift of the device after the repetitive avalanche current stress is highly dependent on the FLRs design, which determines the distributions of the surface electric field and avalanche current at avalanche condition. It is proved that the uniform surface electric field distribution of the FLRs structure at avalanche condition is helpful for the device achieve to achieve better BV shift robustness on the repetitive avalanche current stress. Additionally, the FLRs structure, which has smaller S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> and enough N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> , can present both higher BV and excellent BV shift robustness on the repetitive avalanche current stress.

Demonstration of Avalanche and Surge Current Robustness in GaN Junction Barrier Schottky Diode With 600-V/10-A Switching Capability

In this letter, we achieved significantly enhanced avalanche ruggedness and surge current capability in GaN junction barrier Schottky (JBS) diode for highly reliable power operation. Based on the selective Mg-ion implantation technology, the GaN JBS diode obtains superior electrostatic performances, including 830-V breakdown voltage, 150-mΩ specific on-state resistance, and 0.5-V turning on voltage. Meanwhile, zero reverse recovery behaviors are observed even under extreme switching conditions of 600 V/10 A. During the reliability evaluation in the inductive load circuits, crucial avalanche capability with avalanche breakdown voltage over 965 V, avalanche energy up to 57.8 mJ, and more than 10 000 repetitive avalanche breakdown events are demonstrated. Together with the surge current tolerance up to 65 A and surge energy of 6.0 J, a large safe-operation-area under both forward and reverse inductive spikes is realized for the GaN-based rectifier.

Investigations on the Resistance Reduction Effect of Double-Trench SiC MOSFETs under Repetitive Avalanche Stress

The unexpected resistance reduction effect of double-trench SiC MOSFETs under repetitive avalanche stress is investigated in this work. After enduring repetitive avalanche stress, the ON-state drain-source resistance (Rdson) of the device decreases. With the help of TCAD simulations, the dominant mechanism is proved to be the injection of positive charges into the gate trench bottom oxide, which is almost irreversible under zero-voltage bias condition at room temperature. For the injected positive charges attract extra electrons just beneath the gate trench bottom, where the carriers pass through under ON state, the resistivity there is reduced, improving the conduction capability of the device. Moreover, an optimization method is proposed. Since the impact ionization rate (I.I.) and the vertical oxide electric field (E⊥) along the gate trench bottom oxide interface contribute to the injection of positive charges, it is recommended to make the bottom oxide thicker to suppress this effect.

Performance Degradation of Automotive Power MOSFETs Under Repetitive Avalanche Breakdown Test

Avalanche ruggedness is one of the key factors for safe and reliable power converters deployed in various automotive subsystems. In this article, the avalanche capability of power MOSFETs is tested under different repetitive avalanche conditions to differentiate the die degradation and package degradation. While examining the degradation mechanisms, the corresponding electrical parameter shifts are analyzed to better understand the structural changes and root causes and identify potential precursors for condition monitoring. For this purpose, a high-resolution and cost-effective nanosecond current pulse generator (CPG) is designed. Due to the high-resolution pulsewidth modulation function of a digital signal processor (DSP), short current pulses can be generated in the order of 100 ps where the magnitude and duration of the current pulsewidth can be adjusted precisely. During the experiments, power MOSFETs are stressed under two different pulsewidths. It is observed that the ON-state resistance gradually increases in both cases, yet the roots of the degradations are different. The die degradation and package degradation are responsible for the changes in short pulse and long pulse, respectively. In the short pulse case, some devices show saturation in drain leakage current and ON-state resistance, while some others show a significant threshold voltage drop, which leads to a noticeable shift of transfer and output characteristics. The electrical parameter shifts indicate a possible gate degradation after the device aging. At the end of the tests, failure analyses are conducted on both devices under test (DUTs) under different stress conditions, revealing different failure mechanisms.

Performance of SiC cascode JFETs under single and repetitive avalanche pulses

In this paper, we investigate the single and repetitive avalanche performance and characteristics of different SiC device technologies including SiC cascode JFETs and SiC Trench MOSFETs. SiC Cascode JFETs exhibit a different failure mode from SiC MOSFETs due to the interaction between the low-voltage (LV) silicon MOSFET and the high-voltage (HV) SiC JFET through the resistance connecting the MOSFET source to the JFET gate. MOSFETs fail in avalanche typically due to parasitic BJT latch-up and/or thermal hot-spotting leading to a source-to-drain short. However, cascode JFETs can fail with the low voltage MOSFET still functional and a low resistance measured between the cascode terminals. The failure point of SiC Cascode JFETs in avalanche is therefore not clearly identifiable and the failure criteria will have to be reassessed. Measurements and simulations show that the connection between the JFET gate and the MOSFET source influences the avalanche duration and avalanche power. Finite element simulations show that increased leakage through the gate resistance of the SiC JFET at higher temperatures causes delayed transients in the VDS turn-OFF. Hence, the result is low-voltage avalanche turn-OFF where only the LV silicon MOSFET goes into avalanche and the JFET goes into linear mode. SiC Cascode JFETs show reduced performance under repetitive avalanche due to degradation of the JFET gate resistance and increased linear mode conduction of the SiC JFET. Failure analysis proves that the low voltage silicon MOSFET is unaffected while the avalanche current flows through the SiC JFET gate which appears to be shorted.

Modeling Avalanche Induced Degradation for 4H-SiC Power MOSFETs

In this letter, a model that predicates the degradation of 4H-SiC power metal-oxide-semiconductor field-effect transistors under repetitive avalanche stress is proposed. Since positive charges are injected into the gate oxide interface of the JFET region, the gate-drain capacitance $(C_{gd})$ is chosen as the targeted parameter to quantify the avalanche induced degradation. The relationship between the increment of the $C_{gd}$ and the injected charge density is calculated and validated to demonstrate the rationale of the model. It is found that the increment of $C_{gd}$ has a linear relationship with the logarithm of the total avalanche energy ( E AV) dissipated on the device. Excellent agreement is also achieved between the simulated degraded data and the measured one, further proving the accuracy of the proposed degradation model.

Characteristic and Robustness of Trench Floating Limiting Rings for 4H-SiC Junction Barrier Schottky Rectifiers

In this letter, planar floating limiting rings (FLRs) and trench FLRs with different trench depths for the 4H-SiC junction barrier Schottky (JBS) rectifiers are analyzed and compared with simulations and experiments. Compared with the planar FLRs, the experimental results present that the first ring spacing window that termination efficiency exceeds 80% of the parallel plane breakdown voltage (BV) can be widened and termination area can be reduced at the same BV by adopting the trench FLRs. The simulations also indicate that there is an optimal trench depth for the trench FLRs and a smaller sidewall angle can achieve better device performance. Additionally, the repetitive avalanche current stress measurements imply that the trench FLRs has better robustness regarding the BV shift, achieving better device reliability.

Investigation of the avalanche ruggedness of SiC MPS diodes under repetitive unclamped-inductive-switching stress

State of the art freewheeling diodes are connected antiparallel with a switch like IGBT or MOSFET and for latter also with the internal body diode. The diodes have to be rugged enough to overcome temporary overvoltage and overcurrent conditions during transient operation. SiC merged pin Schottky (MPS) diodes are one of the superior contenders and thus it is essential to make investigations under high avalanche energy. In this work, an avalanche ruggedness of 20 A/1.2 kV SiC MPS diodes was investigated far beyond the specified maximum ratings of the device under unclamped inductive switching (UIS) measurement. The function of avalanche energy versus applied inductance was investigated under single event avalanche stress. The reliability under high repetitive avalanche energy was studied in detail. A forward voltage drift, change in the Schottky junction voltage and increase in the leakage current was observed after the high repetitive avalanche stress far beyond the safe operating area. Detailed failure analysis was made, focusing on the degradation of the metallization and possible stacking faults (SFs) in the SiC bulk. Furthermore, the temperature was determined as a function of the blocking voltage during avalanche stress.

Avalanche Robustness of 4600 V SiC DMOSFETs

A comprehensive investigation of the operating limits and failure modes for 4600 V/7.78 mm2 SiC DMOSFETs under unclamped inductive switching (UIS) conditions is presented. Maximum single-pulse avalanche energies (EAS) as high as 1.07 J (13.75 J/cm2) and avalanche withstand times (tAV) as high as 71 μs are recorded. The variation of EAS and tAV with load inductance (or avalanche current) is quantified. Stability of the key DMOSFET performance characteristics including RDS,on, VTH, body-diode, gate/drain leakage currents and terminal capacitances under both single-pulse and repetitive (up to 1000 shots) avalanche conditions are examined. Different failure locations confined within the active area of the DMOSFETs are identified after avalanche failure for either low or high EAS failed devices and a tentative model to explain the failure physics is presented.

Comprehensive Investigations on Degradations of Dynamic Characteristics for SiC Power &lt;sc&gt;MOSFET&lt;/sc&gt;s Under Repetitive Avalanche Shocks

In this work, degradations of dynamic characteristics for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, gate capacitance versus gate voltage ( Cg – Vg ) measurement, and three-terminal charge pumping test, the main damaged position is demonstrated to be the SiC/SiO2 interface along junction FET (JFET) region instead of the body diode where most of the avalanche current passes through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above the JFET region. Since the channel region and the main junction of body diode are not seriously damaged by the avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath the JFET region gets thinner, resulting in the increase of gate-drain capacitance ( C gd) under low drain-source voltage ( V ds) bias condition. It further takes responsibilities for the increments in input capacitance ( Ciss ), output capacitance ( Coss ), and reverse transfer capacitance ( Crss ). Moreover, it results in the extension of Miller plateau. Therefore, the increase of gate charge and delay of turn- off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn- on and turn- off dissipated energies after different unclamped-inductive-switching stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.

Thermal Analysis Approach for Predicting Power Device Lifetime

The purpose of this paper is to predict the device lifetime under a power cycling test by a simulation method that is based on a distributed self-heating SPICE model. Correlation between numeric extrapolation and experimental data is done by considering the Repetitive Avalanche test, a particular active temperature cycling that evaluates the ruggedness of a power device. The considered failure mechanism is due to front metal aging that produces contact resistance degradation. This phenomenon is strongly dependent on temperature, and by the proposed simulation tool, validated with experimental data, it is possible to evaluate the accurate temperature map and, consequently, predict the lifetime.