Reoxidation Annealing Research Articles

SiC/SiO2 interface properties formed by low-temperature ozone re-oxidation annealing

We propose an ECR ozone plasma re-oxidation annealing (ROA) method that can introduce high-concentration and high-reactivity O atoms to eliminate defects near the SiC/SiO 2 interface with low temperature (400 °C). This method can more effectively improve the electrical performance of SiC MOS capacitors compared with other ROA methods, including O 2 , O 3 and O 2 plasma ROA methods. Secondary ion mass spectroscopy (SIMS), atomic force microscope (AFM) and X-ray photoelectron spectroscopy (XPS) are performed. Results indicate that the O3P-ROA can evidently re-oxidize near-interface defects, which optimize near-interface properties, including the elemental distribution of the near-interface region and the morphology of the SiC/SiO 2 interface. In addition, the effects of temperature and oxygen element on near-interface properties of SiC MOS capacitors are discussed in this paper.

Low-temperature re-oxidation of near-interface defects and voltage stability in SiC MOS capacitors

Abstract We proposed a solution to improve the interface property and voltage instability of silicon carbide metal–oxide–semiconductor (SiC MOS) capacitors by eliminating near-interface defects with a single oxygen element. Results indicated that the quality of the silicon dioxide (SiO2) film and SiC/SiO2 interface and the voltage stability of SiC MOS capacitors were simultaneously improved by the proposed process. The mechanism underlying the improvement in the electrical performance of SiC MOS capacitors by oxygen plasma re-oxidation annealing (OP-ROA) could be elaborated by analysing the results of secondary ion mass spectroscopy and X-ray photoelectron spectroscopy. We believe that the OP-ROA process can eliminate C- and Si-related defects and silicon oxycarbide (SiOxCy) and reduce the thicknesses of the interface–transition region, thereby decreasing relative Si and C contents near the SiC/SiO2 interface. The evolution of C-related defect structures was simulated through density functional theory calculation, which was performed as a supplemental analysis.

Effect of re-oxidation annealing process on the SiO2/SiC interface characteristics

The effect of the different re-oxidation annealing (ROA) processes on the SiO2/SiC interface characteristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance—voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 °C for 30 min, while a large number of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy (XPS) testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.

Effects of wet-ROA on shallow interface traps of n-type 4H-SiC MOS capacitors

The effects of wet re-oxidation annealing (wet-ROA) on the shallow interface traps of n-type 4H-SiC metal—oxide—semiconductor (MOS) capacitors were investigated by Gray—Brown method and angle-dependent X-ray photoelectron spectroscopy technique. The results present the energy distribution of the density of interface traps (Dit) from 0 to 0.2 eV below SiC conduction band edge (EC) of the sample with wet-ROA for the first time, and indicate that wet-ROA could reduce the Dit in this energy range by more than 60%. The reduction in Dit is attributed to the reaction between the introduced oxygen and the SiOxCy species, which results in C release and SiOxCy transformation into higher oxidation states, thus reducing the SiOxCy content and the SiOxCy interface transition region thickness.

Influence of the sintering process on the PTCR effect of chip-type Ba1.022–x Sm x TiO3 ceramics prepared by the reduction sintering-reoxidation method

We investigated the effects of sintering temperature and reoxidation annealing on the positive temperature coefficient of resistance (PTCR) effect of Ba1.022–xSmxTiO3 ceramics that were sintered at 1,180–1,260 °C for 30 min in a reducing atmosphere and reoxidized at 800 °C for 1 h. Results indicated that the room-temperature (RT) resistivity and resistance jump of the ceramics decreased with increasing sintering temperature; moreover, the samples exhibited a remarkable PTCR effect with a resistance jump of 3.3 orders of magnitude and achieved a low RT resistivity of 374.4 Ω cm at a lower sintering temperature. Furthermore, the higher grain-boundary resistivity of the ceramics obtained at a high reoxidation temperature after sintering at low temperature was estimated using an impedance analyzer. In addition, the voltage versus current behavior was investigated in present study.

Fabrication of a P-Channel SiC-IGBT with High Channel Mobility

We fabricated and characterized an ultrahigh voltage (>10kV) p-channel silicon carbide insulated gate bipolar transistor (SiC-IGBT) with high channel mobility. Higher field-effect channel mobility of 13.5 cm2/Vs was achieved by the combination of adopting an n-type base layer with a retrograde doping profile and additional wet re-oxidation annealing (wet-ROA) at 1100°C in the gate oxidation process. The on-state characteristics of the p-channel SiC-IGBT at 200°C showed the low differential specific on-resistance of 24 mΩcm2 at VG = -20 V. The forward blocking voltage of the p-channel SiC-IGBT at 25°C was 10.2 kV a the leakage current density of 1.0 μA/cm2.

Effect of reoxidation annealing on the PTCR behaviour of multilayer Nb5+-doped BaTiO3 ceramics with a Ni internal electrode

The effects of reoxidation annealing on the electrical properties and the positive temperature coefficient of resistance (PTCR) effects of multilayer Ba1.005(Ti1−x Nbx)O3 (BTN) ceramics sintered at different temperatures from 1100 to 1160 °C for 2 h in a reducing atmosphere and reoxidized at various temperatures in the range 500–900 °C were investigated. The results indicated that the room-temperature (RT) resistance of the BTN ceramics reoxidized at different temperatures first increased slowly and then quickly with the increase in the reoxidation temperature. Meanwhile, the resistance jump of the samples increased first and then decreased with the increase in the reoxidation temperature. In addition, the PTCR effect could be improved by prolonging the reoxidation time. Finally, the samples reoxidized at a low temperature of 600 °C after sintering at 1160 °C in a reducing atmosphere exhibited a significant PTCR effect, with a resistance jump of 3.5 orders of magnitude, along with a low RT resistance of 0.38 Ω. Additionally, the influences of the reoxidation temperature and time on the grain resistance and grain-boundary resistance were investigated using complex-impedance spectroscopy.

Effect of Gate Wet Reoxidation on Reliability and Channel Mobility of Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated on 4H-SiC(000-1)

The channel mobility and oxide reliability of metal-oxide-semiconductor field-effect transistors (MOSFETs) on 4H-SiC (0001) carbon face were investigated. The gate oxide was fabricated by using dry-oxidized film followed by pyrogenic reoxidation annealing (ROA). Significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. Furthermore, the field-effect inversion channel mobility (μFE) of MOSFETs fabricated by using pyrogenic ROA was as high as that of conventional 4H-SiC (0001) MOSFETs having the pyrogenic-oxidized gate oxide. It is suggested that the pyrogenic ROA of dry oxide as a method of gate oxide fabrication satisfies both channel mobility and oxide reliability on 4H-SiC (0001) carbon-face MOSFETs.

Effect of Postoxidation Annealing on Reliability of Thermal Oxides Grown on n-Type 4H–SiC(0001) Wafer

The effects of two types of postoxidation annealing (POA) techniques on the reliability of thermal oxides grown on a 4H–SiC(0001) wafer have been investigated. Hydrogen POA at a high temperature of 800 °C is carried out for 30 min after dry oxidation at 1200 °C and it results in an improvement of the insulating properties of thermal oxides. The mode values of the field-to-breakdown (EBD) and charge-to-breakdown (QBD) of thermal oxides prepared by high-temperature hydrogen POA are 10.6 MV/cm and 0.39 C/cm2, respectively. On the other hand, pyrogenic reoxidation annealing (ROA) with a water vapor content above 25% at 950 °C for 180 min adversely affects the reliability of thermal oxides. Also, it is found that the reliability of thermal oxides on a 4H–SiC wafer prepared by pyrogenic ROA degrades with an increase in water vapor content in wet ambient.

Fabrication of Double Implanted (0001) 4H-SiC MOSFETs by using Pyrogenic Re-Oxidation Annealing

Fabrication of Double Implanted (0001) 4H-SiC MOSFETs by using Pyrogenic Re-Oxidation Annealing

A High Voltage (1,750V) and High Current Gain (β=24.8) 4H-SiC Bipolar Junction Transistor using a Thin (12 μm) Drift layer

This paper reports the first, near theoretical limit breakdown voltage (1,750V) 4H-SiC BJTs with both high DC current gain(24.8) and low specific on-resistance (8.4m Ω·cm 2 at 50A/cm 2 and 12m Ω·cm 2 at 356A/cm 2 ) based on a drift layer of only 12 μm, doped to 8.5x10 15 cm -3 . The high performance is achieved through the use of an optimum single-step junction termination extension (JTE), Al-free base Ohmic contact and wet-oxygen low-temperature re-oxidation annealing. Detailed processing conditions are reported. Room temperature and high temperature current- voltage characteristics are also reported.

Strong dependence of the inversion mobility of 4H and 6H SiC(0001) MOSFETs on the water content in pyrogenic re-oxidation annealing

The inversion channel mobility of 4H and 6H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been evaluated for its dependence on the re-oxidation annealing (ROA) conditions in a wet oxidizing ambient. The wet ambient was supplied by the pyrogenic reaction of hydrogen and oxygen gas (pyrogenic ROA), where the water vapor content (/spl rho/(H/sub 2/O)) was controlled by adjusting the hydrogen/oxygen gas flow rate. Not only the annealing temperature and the time, but also /spl rho/(H/sub 2/O) are found to be the critical parameters for improving channel mobility. As a result, field-effect channel mobilities as high as 47 cm/sup 2//Vs for 4H and 95 cm/sup 2//Vs for 6H-SiC MOSFETs were achieved by pryrogenic ROA treatment with a /spl rho/(H/sub 2/O) of 50%.

Temperature dependence of the magnetic field penetration depth versus oxygen ordering in submicron YBCO particles

The influence of oxygen ordering on the temperature dependence of the magnetic field penetration depth λ is investigated in submicron YBa 2 Cu 3 O 6+ x particles obtained by low-temperature ( T s = 800 − 850°C) synthesis from a sol-gel precursor. Additional OO bonds created at low temperature synthesis hinder the oxygen ordering in Cu(1)O plane despite of its high content ( x > 0.82). Oxygen exchange as well as additional annealing stimulate tetra-ortho transition and oxygen ordering. A wide linear range is observed in λ ab −2 ( T ) for samples with highly disordered oxygen. This is attributed to strong phase fluctuations caused by local strains. A gauge-glass model with random distribution of order parameter phases describes the behavior of λ ab −2 ( T ), revealed at initial stage of the hindered tetra-ortho transition. Transformation of the linear λ ab −2 ( T ) fuction to a quadratic one with oxygen ordering is related to decreasing of local deformations and to transformation from a glass state to the usual superconducting orthophase. Two essentially different ways of oxygen ordering, reoxidation and additional annealing, result in the same final state with a similar power law of λ ab −2 ( T ).