Reliable Resistive Random Access Memory Research Articles

Tunable luminous color of LEDs achieved through integrating reliable multilevel RRAM

We developed a color-modulated light-emitting device (LED) by the integration of a p-GaN/n-ZnO heterojunction with reliable resistive random access memory (RRAM) and demonstrated a multi-function integrated device with the adjustable electroluminescence (EL) color by modulating the injection current according to the multiple resistance states. As a critical foundation of an integrated device, reliable operation was achieved by introducing an AlOx layer into HfOx RRAM as an adjustment of the resistive switching endurance. Eventually, the EL color of LED was effectively regulated by modulating the compliance current of RRAM. Thanks to the high uniformity, this modulated LED may be a promising candidate for the application of low-cost and high-density LED displays without complicated structures and techniques, and it can provide a feasible approach for the realization of multilevel resistance state feedback from varied EL color in the future.

Optimization of the position of TaOx:N-based barrier layer in TaOx RRAM devices

Resistive Random-Access Memory (RRAM) presents a transformative technology for diverse computing and artificial intelligence applications. However, variability in the high resistance state (HRS) has proved to be a challenge, impeding its widespread adoption. This study focuses on optimizing TaOx-based RRAMs by strategically placing a nitrogen-doped TaOx barrier-layer (BL) to mitigate variability in the HRS. Through comprehensive electrical characterization and measurements, we uncover the critical influence of BL positioning on HRS variability and identify the optimal location of the BL to achieve a 2x lowering of HRS variability as well as an expanded range of operating voltages. Incremental reset pulse amplitude measurements show that the TaOx:N maintains a low HRS variability even at higher operating voltages when the position of the BL is optimized. Our findings offer insights into stable and reliable RRAM operation, highlighting the potential of the proposed BL to enhance the functionality of TaOx-based RRAMs and elevate overall device performance.

Improved switching stability in SiNx-based RRAM by introducing nitride insertion layer with high conductivity

In this Letter, a Pt/SiNx/TiN/Ta resistive random access memory (RRAM) is proposed, which has low switching voltage, uniform resistance distribution, excellent cycle-to-cycle stability, and excellent nonvolatile performance. As an insertion layer, TiN prevents excessive absorption of nitrogen ions by a Ta electrode and avoids the formation of the unstable metal–semiconductor interface, which significantly reduces cycle-to-cycle variability of SiNx-based RRAM. Due to high conductivity, the TiN layer has a small voltage divider effect when voltage was applied, which helps to achieve low power consumption characteristics. This paper provides a direction for improving performance of nitride-based RRAM, which is useful for further development of highly reliable RRAM.

Understanding the Origin of Unreliable Low-Resistance State During Initialization Process

The main factor hindering the massive employment for resistive random access memory (RRAM) can be ascribed to reliability issues. It has been reported that resistive switching (RS) characteristics were unstable during initial <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}-{V}$ </tex-math></inline-formula> cycles; however, the reason has not been studied yet. In this article, the mechanism for a significant increase in a low-resistance state (LRS) value during the initial cycles has been investigated. In this article, we suggest that the initialization process is actually the formation process of a stable TaOx interface layer between the RS layer and the top electrode (TE). Furthermore, a co-regulation model of the filament-type and the interface-type switching mechanisms on RS behavior is proposed, which explains the complete working process of devices. By reducing the size of the device and increasing the positive stop voltage, the initialization process of the device has been greatly shortened. This article may promote the development of advanced and reliable RRAM devices.

Forming‐Free, Self‐Compliance, Bipolar Multi‐Level Resistive Switching in WO3–x Based MIM Device

AbstractResistive switching (RS) in metal oxides, which offers self‐compliance and multiple resistance states without the requirement of any high voltage forming step, holds the potential of application in selector less high density resistive random access memory (RRAM) devices. Typically, operation of metal oxide‐based RS devices requires the integration of additional oxide layers or circuit elements to achieve current compliance and complicated device architecture for high‐density memory applications. In this study, a self‐compliance, and multi‐level RS is demonstrated that does not require high voltage forming in a single layer non‐stoichiometric WO3–x. This study suggests that high oxygen vacancy (VO) concentration in the pristine WO3–x layer leads to its forming‐free filamentary switching characteristics, whereas reversible formation and annihilation of an oxygen‐rich region in the filament at the WO3–x/Pt junction has been envisaged to be responsible for self‐compliance set and voltage controlled multiple reset resistance states. The results demonstrate non‐stoichiometric WO3–x with an active metal/oxide interface permeable to reversible oxygen migration can pave the way for producing high density, reliable RRAM devices.

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source

Physically unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with a wide range of applications in the Internet of Things (IoT). In recent years, novel PUF techniques based on resistive switching mechanism in various emerging nonvolatile memories have demonstrated superior performance on reliability and integration density. In this work, a resistive random access memory (RRAM)-based PUF chip with 8-kb capacity is developed. Two operation modes, namely differential mode and median mode, are embedded on chip. To implement these modes, a current sampling-based sense amplifier is designed to distinguish the current values of the PUF cells and the reference cell. In addition, a split-resistance scheme is proposed to enhance the PUF's reliability significantly. The experiment results show that the differential PUF exhibits excellent performance with native bit error rate (N-BER) below 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> and inter-Hamming distance (inter-HD) of 49.99%. In the meanwhile, the reconfigurability of PUF challenge-response pairs (CRPs) is demonstrated with 49.77% and 47.29% reconfigure-Hamming distance (reconfigure-HD) in the median mode and the differential mode, respectively.

Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit

Resistive random-access memory (ReRAM) has several attractive features such as high storage density and high switching frequency with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance. Hence, an error-correcting code (ECC) circuit is indispensable for realizing reliable ReRAM storage. Accordingly, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with high-frequency write operations are implemented using the conventional CMOS technology and the other blocks are implemented using the memristors to maintain a balance between the area overhead and reliability. Through numerical experiments, we demonstrate that the proposed ECC circuit achieves smaller area and higher reliability than the full memristor-based ECC circuits and achieves much smaller area while preserving the reliability compared with the full CMOS-based ECC circuits.

Bilayer Dielectrics for RRAM Devices

To implement low power and highly reliable resistive random-access memory (RRAM) devices, suitable multi-layer dielectric materials are required. This consists of a switching layer, the oxygen vacancy medium, to form the filament and an oxygen vacancy deficient layer, such as Al2O3 to control the filament rupture. This work explores several different bilayer structures using different dielectrics, electrode materials and processing conditions to reduce power consumption during forming, set and reset operations and to enhance endurance with a large Roff/Ron value for RRAM application. Several transition metal dielectrics (HfAlO2 or HfZrO2) were used as the switching layer on a thin Al2O3. By comparing the forming voltage values, Roff/Ron values and both set and reset power consumption, optimized performance was derived.

Modeling and simulation of Cu diffusion and drift in porous CMOS backend dielectrics

With the advent of porous dielectrics, Cu drift-diffusion reliability issues in CMOS backend have only been exacerbated. In this regard, a modeling and simulation study of Cu atom/ion drift-diffusion in porous dielectrics is presented to assess the backend reliability and to explore conditions for a reliable Resistive Random Access Memory (RRAM) operation. The numerical computation, using elementary jump frequencies for a random walk in 2D and 3D, is based on an extended adjacency tensor concept. It is shown that Cu diffusion and drift transport are affected as much by the level of porosity as by the pore morphology. Allowance is made for different rates of Cu dissolution into the dielectric and for Cu absorption and transport at and on the inner walls of the pores. Most of the complex phenomena of the drift-diffusion transport in porous media can be understood in terms of local lateral and vertical gradients and the degree of their perturbation caused by the presence of pores in the transport domain. The impact of pore morphology, related to the concept of tortuosity, is discussed in terms of “channeling” and “trapping” effects. The simulations are calibrated to experimental results of porous SiCOH layers of 25 nm thickness, sandwiched between Cu and Pt(W) electrodes with experimental porosity levels of 0%, 8%, 12%, and 25%. We find that porous SICOH is more immune to Cu+ drift at 300 K than non-porous SICOH.

Improvement of HfOx-Based RRAM Device Variation by Inserting ALD TiN Buffer Layer

In this letter, the impacts introduced by oxygen-scavenging metal (Ti), including forming voltages variation and resistances dispersion in high/low states of HfO x -based RRAM devices, were investigated. Based on experiments, it is concluded that Ti atoms during physical vapor deposition process can randomly penetrate into the bulk of HfO x and are intended to randomly create the initial oxygen vacancies, thus causing the performance degradation. Moreover, a novel structure with an atomic layer deposition-TiN buffer layer inserted between oxygen-scavenging Ti and HfO x layers was proposed and experimentally demonstrated to reduce the impacts of Ti penetration, which further improves vacancy-creating approach. It was experimentally verified that with the help of incorporating a TiN buffer layer, the uniformity of switching parameters, such as forming voltage and resistance, was effectively improved. The understanding and improvement of device variation caused by oxygen-scavenging metal in oxides-based resistive random access memory (RRAM) are useful for further development of highly reliable RRAM technology.

Toward reliable RRAM performance: macro- and micro-analysis of operation processes

Resistive random access memory (RRAM) technology promises superior performance and scalability while employing well-developed fabrication processes. Conductance in insulating oxides employed in RRAM devices can be strongly affected by atomic-level changes that makes cell switching properties extremely sensitive to operation conditions inducing local structural modifications. This opens an opportunity to condition the memory cell stack by forming a conductive filament capable of high frequency, low energy switching. Certain materials with pre-existing conductive paths, in particular some polycrystalline oxides, like hafnia, are shown to respond well to this approach. For this class of materials, the concept of ultra-fast pulse technique as an ultimate method for assessing RRAM switching capabilities in circuitry operations is discussed. Hafnia-based cells demonstrate compliance-free (1R) forming with no current overshoot, low operation currents, and reduced variability.

A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System

In this paper, we study the 1-selector1-resistor (1S1R) cross-point resistive random access memory (ReRAM) array because of its high density, fast access time, and ultralow stand-by power. Specifically, we focus on an access scheme where a data line is parallelly accessed from multiple subarrays with multibits accessed per subarray. A direct implementation of such a scheme has high energy efficiency but lower reliability compared with a single bit per subarray baseline scheme. So this paper proposes a low cost multilayer approach to improve energy-efficiency of multibits per access scheme without compromising reliability. At the cell level, we show how proper choices of bit-line and source-line voltage and SET recovery help reduce error rate by ten times. At the system level, we propose a new rotated multiarray access scheme where the average error rate of every accessed data line is one order of magnitude lower than the worst case, making it possible to achieve block failure rate of 10-10 with a simple Bose, Chaudhuri, and Hocquenghem t = 4 code. We show that for a 1 GB 1S1R ReRAM, the proposed approach can reduce energy by 41% with 2% extra area while maintaining latency and reliability compared with the baseline system.

A long lifetime, low error rate RRAM design with self-repair module**Project supported by the New Century Excellent Talents in University (No. NCET-12-0165) and the National Natural Science Foundation of China (Nos. 61472123, 61272396).

Resistive random access memory (RRAM) is one of the promising candidates for future universal memory. However, it suffers from serious error rate and endurance problems. Therefore, exploring a technical solution is greatly demanded to enhance endurance and reduce error rate. In this paper, we propose a reliable RRAM architecture that includes two reliability modules: error correction code (ECC) and self-repair modules. The ECC module is used to detect errors and decrease error rate. The self-repair module, which is proposed for the first time for RRAM, can get the information of error bits and repair wear-out cells by a repair voltage. Simulation results show that the proposed architecture can achieve lowest error rate and longest lifetime compared to previous reliable designs.

(Invited) Material and Device Design for Practical Application of Highly-Reliable and High-Density ReRAM

Electric-pulse-induced resistance change phenomena in PrCaMnO3 were reported in 2000 [1]. From this finding, Resistive Random Access Memory (ReRAM) using this phenomena attracted both academic and industrial researchers as a promising candidate of next-generation nonvolatile memory. In 2013, we started the world’s first mass-production of ReRAM-embedded micro-controller unit. Among issues to be solved for its practical application, the most fundamental problem was that the mechanism of resistive switching (RS) remained unclear, causing the lack of guide for the design of materials and devices for ReRAMs. Therefore, we investigated the mechanism of RS and considered the appropriate materials and device structures for ReRAM from the viewpoint of device reliability. Based on the clarified RS mechanism, we successfully developed highly-reliable Ta oxide ReRAM. ReRAM cells with top electrode/Ta oxide/bottom electrode was fabricated. Ta oxide was deposited by reactive sputtering. Device structures, RS characteristics and reliability of ReRAMs were evaluated by electrical measurements and physical analyses.In order to elucidate the mechanism of RS, chemical states in ReRAM cells for initial resistance state, high-resistance state (HRS) and Low-resistance state (LRS) were directly observed by hard x-ray photoemission spectroscopy. The ratio of Ta 4d photoemission peaks for Ta sub-oxide (TaOx) to Ta2O5 increases with the decrease in the resistance of ReRAM cells (from Initial to HRS to LRS). This indicates that the mechanism of RS is redox reactions in Ta oxide layer. Based on the RS model, the guidelines for the material selection of oxide and electrode were presented. Oxide material should be bi-stable: The Gibbs free energy for the reaction between oxides with different valence states such as TaO2/Ta2O5should be small. Electrode material should not be easy to oxidize: Standard electrode potential of the electrode metal should be sufficiently higher than that of material constituting the RS oxide [2]. We next investigated the detailed structure of Ta oxide ReRAM and found that the RS locally occurred in small conductive area (Conductive Filament: CF) consisting of oxygen-deficient Ta oxide [3]. Therefore, we evaluated the retention characteristics of Ta oxide ReRAMs focusing on the CF. Experimental results indicate that the retention degradation of LRS/HRS is caused by the oxygen diffusion into/out of CF. From detailed analyses, we clarified that the control of CF characteristics including filament size and the density of oxygen vacancy was the key for the improvement of the reliability [4]. Utilizing these insights, we established the reliability model of Ta oxide ReRAM and successfully started the mass-production of ReRAM. The delivery of higher-density ReRAM is essential for further spread of ReRAM in the market. The following two the issues are inevitable for the realization of higher-density ReRAM; (1) scaling down of ReRAM cells and (2) low-current operation, which may degrade the reliability. Therefore, we addressed these challenges and successfully demonstrated the good array-level reliability with scaled-down cells and low-current operation by controlling the CF from the standpoint of fabrication process and device structure, respectively [5,6].

Cyclic resistive switching effect in plasma electrolytically oxidized mesoporous Pt/TiO2 structures

Understanding the resistive switching phenomenon in metal oxide semiconductors is necessary in producing reliable resistive random access memory and other variable resistance devices. An alternative technique for fabricating resistive switching elements is presented. Using plasma electrolytic oxidation, 10–11μm thick oxide layers were galvanostatically grown on Ti substrates in a 3M H2SO4 electrolyte. Analysis of the TiO2 layer by SEM, AFM, and XRD found the mesoporous titania surface to have a high ratio of rutile to anatase phases. The samples demonstrated pinched I–V hysteresis attributed to the resistive switching effect, when subjected to cyclic loading (±2.5, 1.6, 0.7V; 23–736μHz) at room temperature. Ratio with magnitude of 6 is reported for the resistance switching effect during 1.6V 368μHz loads.

Performance Analysis of Memristor Models for RRAM Cell Array Design using SILVACO EDA

Resistive Random Access Memory (RRAM) is gaining attention as one of the prominent contenders to replace the conventional memory technologies such as SRAM, DRAM and Flash. This emerging memory uses scaled CMOS devices (22 nm or less) to form the peripheral circuits such as decoder and sense amplifier; while a non-CMOS device known as memristor is used to form the cell array. Although potentially becoming the main future memory, RRAM is anticipated to be impacted by the high manufacturing defect density that in turn might lead to quality and reliability problems. This paper presents the initial work towards producing a high quality and reliable RRAM devices. A design and simulation of three memristor SPICE models published in prominent literatures were performed using Silvaco EDA simulation tool. The aim is to identify the optimal model to be used in our RRAM design, which is based on 22 nm CMOS technology. Performance analysis shows that the model proposed by D. Biolek is suitable to be used in our RRAM design.