Reliability Of Wafer Level Chip Scale Package Research Articles

Impact of Microstructure Evolution on the Long-Term Reliability of Wafer-Level Chip-Scale Package Sn–Ag–Cu Solder Interconnects

The interaction between the continuous microstructure evolution during thermal cycling and the long-term reliability of wafer-level chip-scale packages (WLCSPs) with Sn-1.0Ag-0.5Cu (wt%) (SAC105), Sn-3.0Ag-0.5Cu (wt%) (SAC305), and Sn-3.9Ag-0.6Cu (wt%) (SAC396) solder ball interconnects were investigated. Three different body-sized WLCSP with three different solder alloys on three different board thickness were thermally cycled from 0 °C to 100 °C with 10 min of dwell time, and the microstructure evolution and their impact to the life cycle numbers were identified. Based on both experimental and calculated data, higher Ag contained solder alloys perform better in thermal cycling. However, the comparison between the calculated life cycle and the experimental results revealed mismatch, which is due to the localized recrystallization areal fraction differences. Smaller die WLCSP with 4×4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 3.2×3.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> exhibited a large difference in expected life cycle numbers. The calculated life cycles expected a lower cycle number with thicker boards for both SAC105 and SAC396 WLCSPs, but the experimental data revealed an increase with SAC105 and a similar level of life cycle time with SAC396, for thicker boards. A widely distributed areal fraction of damage accumulation through the solder rows were observed in SAC105 compared with higher Ag solder alloy joints, which show localized damage accumulation at corner joints. The difference of areal recrystallization distribution explains the difference between SAC105 and SAC305/396 thermal cycling behavior between the calculated and experimental thermal cycling results.

Understanding and Improving Reliability for Wafer Level Chip Scale Package: A Study Based on 45nm RFSOI Technology for 5G Applications

Wafer level chip scale package (WLCSP) is true chip scale package with low cost by eliminating package substrate. The direct chip-to-board attach through solder joints provides low interconnect inductance and resistance, as well as improved thermal performance. These properties make WLCSP a packaging format well suited for 5G radio frequency (RF) applications where minimized package size and parasitics as well as thermal performance are critical. Due to the dissimilar properties between chip and board, the reliability of WLCSP can be challenging. This article reports a reliability study of WLCSP using 45nm RFSOI technology for 5G RF applications. Dedicated test chips and boards were designed and used for board level reliability tests. The test vehicles passed bHAST and drop test, whereas it is found that temperature cycling on board (TCoB) is challenging for solder joint reliability in some cases. Thorough tests were carried out based on Kelvin test on specially designed individual bump and bump pair structures and developed fail criterion. Finite element modeling was adopted to simulate the reliability performance in different configurations. The impact on reliability performance from bump depopulation, die thickness, bump size, UBM to board pad alignment, and board wiring trace were thoroughly investigated. Based on comprehensive testing and deep understanding of the failure mechanisms, design optimizations for chip, board and interconnect were implemented. WLCSP reliability was significantly improved.

Impact of Isothermal Aging and Sn Grain Orientation on the Long-Term Reliability of Wafer-Level Chip-Scale Package Sn–Ag–Cu Solder Interconnects

The interaction between isothermal aging and the long-term reliability of wafer-level chip-scale packages with Sn-3.0Ag-0.5Cu (wt%) solder ball interconnects is investigated. On isothermally aging at 100 and 150°C for 500 h and then thermally cycling from 0 to 100°C with 10 min of dwell time, the lifetime of the package is reduced by approximately 29%, depending on the aging condition. The microstructural evolution is observed during thermal aging and thermal cycling using orientation image microscopy. A Sn grain orientation structure transformation is observed. Different mechanisms after aging at various conditions are identified, and their impacts on the fatigue life of solder joints discussed.

Computational Assessment of the Effects of Temperature on Wafer-Level Component Boards in Drop Tests

The drop reliability of wafer-level chip-scale package (WL-CSP) component boards used in portable devices was studied by employing mechanical shock loads (JESD22-B111 standard) at different temperatures. The drop tests were carried out at room temperature (23 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C), 75 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C, 100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C, and 125 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C. The elevated temperatures were achieved by integrated heater elements in the components. The number of drops-to-failure increased significantly with increasing temperature. The physical failure analysis revealed that the outermost solder interconnections at the four corners of the components failed from the component side. At room temperature, the cracks propagated solely along the intermetallic layers but the increase of testing temperature progressively changed their propagation paths from the intermetallic layers into the bulk solder. Since the temperature 1) decreases the strength and elastic modulus of solders, 2) diminishes the stiffness of printed wiring boards, and 3) introduces thermally induced stresses, the finite-element method was employed to evaluate their combined effects. The calculations showed that due to the increases in testing temperature, the peeling stress is reduced markedly, while the equivalent plastic strain is only slightly increased at the interfacial regions of the solder interconnections. The reduction of the stresses increases the proportion of the bulk solder cracking relative to the cracking of the intermetallic layers and therefore the number of drops-to-failure increases as a function of increasing test temperature.

Structural design optimization for board-level drop reliability of wafer-level chip-scale packages

In this paper, the Taguchi optimization method is applied to obtain the optimal design in enhancing board-level drop reliability of a wafer-level chip-scale package (WLCSP) under JEDEC drop test condition B, which features a half-sine impact acceleration pulse with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. An L 9 (3 4) orthogonal array is arranged for the optimization of four control factors that involve compositions of solder alloys and thickness of die and polyimide passivation layers. The submodeling technique capable of dealing with path-dependent features, including elastoplastic responses of solder joints and structural nonlinearity under drop impacts, is applied so that delicate structures of passivation, under bump metallurgy (UBM), and redistribution line (RDL) in a WLCSP package can be taken into account. Effects of these control factors on the drop reliability of WLCSP are compared and ranked.

Cyclic bending reliability of wafer-level chip-scale packages

In this paper, both experimental and numerical studies are conducted to investigate board-level reliability of wafer-level chip-scale packages under four-point cyclic bending conditions that combine different deflection amplitudes and excitation frequencies. In addition to the fatigue lives of the test vehicle, locations and modes of fractured solder joints are observed. In the numerical modeling, inertia forces along with rate-dependent material properties of the solder joints are considered in order to capture frequency-dependent characteristics of this particular test methodology. Through the dynamic finite element analysis, plastic strain energy densities accumulated per bending cycle within the critical solder joint are calculated and together with the experimental results, parameters for the Morrow fatigue model are calibrated.

Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages

In this paper we study board-level thermomechanical reliability of a wafer-level chip-scale package subjected to an accelerated thermal cycling test condition. Different control factors are considered for a robust design towards enhancement of the thermal fatigue resistance of solder joints. These factors include diameter, pitch, and standoff of the solder joints, size of the solder connection opening on the die side, thickness of the pad on the test board, thickness of the test board, and dimension of the die. The Taguchi method along with the technique of analysis of variance are applied in the robust design process. Importance of these factors on the thermomechanical reliability of the package is ranked and the resulting robust design is further verified.

Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages

We present in this paper parametric studies of board-level reliability of wafer-level chip-scale packages subjected to a specific pulse-controlled drop test condition. Eighteen experiment cells, constructed by varying joint pitch, die thickness, and die size, are proposed and examined numerically. The transient analysis follows the support excitation scheme and incorporates an implicit time integration solver. Numerical results indicate that the drop reliability of the package enhances as the die thickness as well as the die size decreases. Moreover, the package with smaller solder joints and a smaller joint pitch suffers a greater drop reliability concern.

Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study.