Abstract
The drop reliability of wafer-level chip-scale package (WL-CSP) component boards used in portable devices was studied by employing mechanical shock loads (JESD22-B111 standard) at different temperatures. The drop tests were carried out at room temperature (23 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C), 75 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C, 100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C, and 125 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C. The elevated temperatures were achieved by integrated heater elements in the components. The number of drops-to-failure increased significantly with increasing temperature. The physical failure analysis revealed that the outermost solder interconnections at the four corners of the components failed from the component side. At room temperature, the cracks propagated solely along the intermetallic layers but the increase of testing temperature progressively changed their propagation paths from the intermetallic layers into the bulk solder. Since the temperature 1) decreases the strength and elastic modulus of solders, 2) diminishes the stiffness of printed wiring boards, and 3) introduces thermally induced stresses, the finite-element method was employed to evaluate their combined effects. The calculations showed that due to the increases in testing temperature, the peeling stress is reduced markedly, while the equivalent plastic strain is only slightly increased at the interfacial regions of the solder interconnections. The reduction of the stresses increases the proportion of the bulk solder cracking relative to the cracking of the intermetallic layers and therefore the number of drops-to-failure increases as a function of increasing test temperature.
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