Reliability Of Microelectronic Devices Research Articles

Anti-plane Yoffe-type crack in flexoelectric material

This work investigates the deformation and polarization fields around a finite anti-plane shear (mode III) crack growing dynamically under steady-state conditions. The leading tip of this finite crack breaks the material while the trailing tip heals it. This fast moving finite crack (referred to as a rupture “pulse” in the geophysics literature) propagates with a constant velocity and with the mechanical and the electrical fields that remain invariant with respect to an observer moving with the crack-tips. This problem belongs to the first type of steady state crack growth problems according to the classification of Freund. The “prototype” problem which refers to an isotropic, body subjected to fracture under tensile loading was first proposed and solved by Yoffe, while finite cracks (or shear pulses) were also analyzed by Freund and by Rice. In the above cases the material was assumed to be linear elastic. Our analysis extends these studies to flexoelectric materials, and it is both theoretical and numerical. It discusses the asymptotic structure of the crack-tip displacement and the polarization fields; it calculates the dynamic energy release rate and presents their dependence on crack-tip velocity. Comparisons are made to the available, classical, elasto-dynamic solutions and to the static case. The influence of the electrical properties of the material on strengthening is also analyzed. Dynamic fracture of flexoelectric materials is of relevance to both the study of earthquake source mechanics and to the analysis of the reliability of micro-electronic devices. This is because both rocks and ceramics are flexoelectric. Indeed, during earthquake rupture processes, dynamic, in-plane shear (Mode-II) and out of plane shear (Mode-III), cracks propagate along faults and exhibit both mechanical and electrical polarization signatures. At an entirely different length scale, flexoelectric ceramics are currently used as sensors and transducers and can experience dynamic shear failure along interfaces when subjected to dynamic loading (e.g. impact.). Failure by dynamic fracture can be detrimental to both their mechanical reliability and electrical functionality.

Diffusion Barrier Performance of Ni-W Layer at Sn/Cu Interfacial Reaction.

As the integration of chips in 3D integrated circuits (ICs) increases and the size of micro-bumps reduces, issues with the reliability of service due to electromigration and thermomigration are becoming more prevalent. In the practical application of solder joints, an increase in the grain size of intermetallic compounds (IMCs) has been observed during the reflow process. This phenomenon results in an increased thickness of the IMC layer, accompanied by a proportional increase in the volume of the IMC layer within the joint. The brittle nature of IMC renders it susceptible to excessive growth in small-sized joints, which has the potential to negatively impact the reliability of the welded joint. It is therefore of the utmost importance to regulate the formation and growth of IMCs. The following paper presents the electrodeposition of a Ni-W layer on a Cu substrate, forming a barrier layer. Subsequently, the barrier properties between the Sn/Cu reactive couples were subjected to a comprehensive and systematic investigation. The study indicates that the Ni-W layer has the capacity to impede the diffusion of Sn atoms into Cu. Furthermore, the Ni-W layer is a viable diffusion barrier at the Sn/Cu interface. The "bright layer" Ni2WSn4 can be observed in all Ni-W coatings during the soldering reflow process, and its growth was almost linear. The structure of the Ni-W layer is such that it reduces the barrier properties that would otherwise be inherent to it. This is due to the "bright layer" Ni2WSn4 that covers the original Ni-W barrier layer. At a temperature of 300 °C for a duration of 600 s, the Ni-W barrier layer loses its blocking function. Once the "bright layer" Ni2WSn4 has completely covered the original Ni-W barrier layer, the diffusion activation energy for Sn diffusion into the Cu substrate side will be significantly reduced, particularly in areas where the distortion energy is concentrated due to electroplating tension. Both the "bright layer" Ni2WSn4 and Sn will grow rapidly, with the formation of Cu-Sn intermetallic compounds (IMCs). At temperatures of 250 °C, the growth of Ni3Sn4-based IMCs is controlled by grain boundaries. Conversely, the growth of the Ni2WSn4 layer (consumption of Ni-W layer) is influenced by a combination of grain boundary diffusion and bulk diffusion. At temperatures of 275 °C and 300 °C, the growth of Ni3Sn4-based IMCs and the Ni2WSn4 layer (consumption of Ni-W layer) are both controlled by grain boundaries. The findings of this study can inform the theoretical design of solder joints with barrier layers as well as the selection of Ni-W diffusion barrier layers for use in different soldering processes. This can, in turn, enhance the reliability of microelectronic devices, offering significant theoretical and practical value.

First-principles investigation of Cu/Ti-TM/Si (TM=W, Ru) interfaces: Role of Ti-TM binary alloys as diffusion barrier layers

This study employs first-principles calculations to investigate the role of Ti-TM (TM=W, Ru) binary alloys as diffusion barrier layers in Cu/Ti-TM/Si interfaces, which are critical for enhancing the performance and reliability of microelectronic devices. The calculated results reveal that TiRu and Ti4W12 alloys exhibit exceptional stability and low contact resistance, outperforming traditional Cu/Si interfaces. The introduction of these alloys into the interface structure results in a reduced Cu s-d coupling effect, which is pivotal for inhibiting Cu diffusion. Additionally, the presence of pseudogap features and enhanced electron distribution at the interface indicate strong atomic interactions, contributing to the formation of covalent bonds and further improving barrier properties. The findings suggest that TiRu and Ti4W12 alloys are promising candidates for diffusion barrier layers, offering a balance of low contact resistance, thermal stability, and effective Cu diffusion inhibition. Therefore, from the results, it is concluded that the formation of the new interface structure will improve performance in various aspects, and thus the strategy can be applied in various directions, such as new energy materials, electronic materials, and so on. In addition, the combination of the previous work and the present work suggests that Ti-based alloys have the potential to be used as diffusion barrier materials.

Facile and Scalable Strategy for Fabricating Highly Thermally Conductive Epoxy Composites Utilizing 3D Graphitic Carbon Nitride Nanosheet Skeleton.

The application of high-performance thermal interface materials (TIMs) for thermal management is commonly used to tackle the problem of heat accumulation, which influences the performance and reliability of microelectronic devices. Herein, a novel three-dimensional (3D) carbon nitride nanosheet (CNNS)/epoxy composite with high thermal conductivity was developed by introducing 3D CNNS skeleton fillers prepared by a facile and scalable strategy assisted by a salt template. Benefiting from the continuous heat transfer pathways formed in the CNNS skeleton, 17.0 wt % 3D CNNS/epoxy composites achieve a superior thermal conductivity of 1.27 W/m·K, which is 6.35 and 1.57 times higher than those of epoxy resin and convention CNNS/epoxy, respectively. With the aid of theoretical model analysis and finite element simulation, the pronounced enhancement effect of the 3D CNNS skeleton on the thermal conductivity of epoxy composites is found to be attributed to the continuous 3D CNNS thermally conductive network, the diminished CNNS-CNNS interfacial thermal resistance, and the effective interfacial interactions between epoxy and CNNS. In addition, the 3D CNNS/epoxy composites possess high electrical insulation and desirable mechanical strength. Therefore, 3D CNNS/epoxy composites are promising TIMs for advanced electronic thermal management.

Controlling diffusion in gold bonding materials for high reliability via microalloying of trace rare earth metals

Diffusion plays a vital role in regulating microstructure evolution and properties of metallic materials. However, understandings of how microalloying affects diffusion kinetics in gold bonding materials remain far from comprehensive, which severely threatens the reliability of microelectronic devices in the big-data era. This problem persists challenging due to enormous difficulty in accurate and cost-effective experimental measurements. Here, first-principle based theoretical computations are performed to explore the control of diffusion at elevated service temperatures by trace rare earth (RE) microalloying in gold bonding materials. We identify the light lanthanides can stably bind excess vacancies and the efficacy to modulate vacancy/solute-vacancy evolution depends on the RE concentrations and ambient temperatures. Above critical doping concentrations, self- and impurity-diffusion can be simultaneously hindered. These findings successfully point to a rational microalloying strategy to withstand heat and a novel perspective on improving the service life-time of microelectronics packaging materials.

Molecular dynamics study of tensile properties of graphene/GaN heterostructures

Graphene/GaN nanocomposites have been widely used in high-power and high-frequency optoelectronic devices. At present, the thermal transport characteristics of graphene/gallium nitride heterostructures have been investigated by many scholars, but their mechanical properties have not been systematically studied. In this paper, the effects of graphene layer number, temperature and interfacial structure on the mechanical properties of graphene/GaN heterostructures were investigated by molecular dynamics method. The mechanical properties of materials were analyzed by failure stress, failure strain and Young’s modulus. The simulation results show that the heterogeneous structure is very sensitive to temperature. When the temperature is set at 2000K, the Young’s modulus of the heterostructure decreases by 25.11% compared with that at 300K, which indicates that the increase of temperature will reduce the mechanical properties of graphene composites, However, when the number of graphene layers increases, the mechanical properties of the heterostructures also improved. With the number of graphene layers is set from 1 layer to 5 layers, the performance of the heterostructure is improved, and its Young’s modulus increases by 48.46%. In addition, the effect of interface structure on the young’s modulus of the heterostructure structure is not obvious, but it will affect the maximum failure stress and maximum failure strain of the material. The mechanical properties of graphene in cross section contact with gallium atom are better than those of nitrogen atom. It is beneficial to improve the reliability of microelectronic devices to control and design heterogeneous structures based on the research results.

(Invited) Micromechanical Aspects of GaN Hemt Performance and Reliability

Performance and reliability of microelectronic devices are governed by the mechanical strain. Typically, strain engineering implies uniformly distributed strain. However, we offer a different perspective by hypothesizing that very small but localized strain (or stress) may have significant impact on the overall behavior of AlGaN/GaN high electron mobility transistors (HEMTs). Micro to nanoscale confined mechanical stress fields may develop unavoidably and are ignored because their spatial average is insignificant. We exploit high resolution techniques such as transmission electron microscopy (TEM) and micro-Raman spectroscopy to spatially resolve the stress field in GaN HEMTs to demonstrate the stress localization and then radiation effects.To study stress localization effects on the global electrical characteristics, we introduced a highly localized strain relief by milling a 20×30 μm2 micro trench about 70 μm deep on the backside of an 800×840 μm2 size HEMT die. The resulting local relaxation of in-plane residual strain was mapped using micro-Raman technique. Our results show that a decrease of only 0.02% strain can decrease the overall output saturation current up to ~20 %. The drop of output current is attributed to reduced two-dimensional electron gas (2DEG) sheet carrier density and electron mobility due to the strain relief in the device layers. However, the mechanistic process of strain relief also causes defect generation at the interfaces, which increases leakage current. Our technique for localized strain re-distribution could be an effective tool to surrogate the influence of inherent localized strain build-up across the channel of electronic devices.To study radiation effects, we exposed the HEMTs to gamma rays (up to 10 megaRads dose at 180 kiloRads per hour). We report the thermal and mechanical responses in terms of the changes in lattice strain and temperature, which were simultaneously characterized by changes in phonon frequency of E2 (high) and A1 (LO) from on- state and unpowered/pinched off reference states. Lower doses of radiation improved the electrical properties, however degradation initiated at about 1 megaRads. We observed about 16% decrease in saturation current and 6% decrease in transconductance at the highest dose. However, leakage current increase by 3 orders of magnitude was the most notable radiation effect. We observed temperature increase by 40% and mechanical stress increase by a factor of three at dose of 10 megaRads compared to the pristine devices. Spatial mapping of mechanical stress along the channel identifies the gate region as mechanically affected area, whereas the thermal degradation was mostly uniform. Transmission electron microscopy showed contrast changes reflecting high vacancy concentration in the gate region. These findings suggest that localized stress (mechanical hotspots) may increases vulnerability to radiation damage by accommodating higher concentration of defects that promote leakage current.Finally, we present experimental results on a novel concept of electron wind force driven room temperature annealing of GaN and SiC devices. This technique was applied on Gamma irradiated HEMT and SiC diodes. We demonstrate full recovery of the HEMTs irradiated to 10 mega-Rads gamma radiation. About 200% performance improvement was recorded for the SiC diodes. Our hypothesis is that mechanical stress waves are instrumental in eliminating interfacial defects.

Local strain modification effects on global properties of AlGaN/GaN high electron mobility transistors

Performance and reliability of microelectronic devices are governed by the mechanical strain within the device layers. Typically, this is studied with uniformly distributed strain applied externally or internally. The focus of this study is on AlGaN/GaN high electron mobility transistors (HEMTs), which is expected to be more sensitive to strain due to its piezo-resistive and piezo-electric nature. Accordingly, we hypothesize that even small but localized strain may have significant impact on the overall behavior of a HEMT. To investigate this hypothesis, we introduce highly localized strain relief by milling a 20 × 30 μm2 micro trench about 70 μm deep on the backside of an 800 × 840 μm2 size HEMT die. The resulting local relaxation of in-plane residual strain was mapped using micro-Raman technique. Our results show that a decrease of only 0.02% strain can decrease the overall output saturation current up to ~20%. The drop of output current is attributed to reduced two-dimensional electron gas (2DEG) sheet carrier density and electron mobility due to the strain relief in the device layers. However, the mechanistic process of strain relief also causes defect generation at the interfaces, which increases leakage current. Our technique for localized strain re-distribution could be an effective tool to surrogate the influence of inherent localized strain build-up across the channel of electronic devices.

Methods for Measuring Thermal Conductivity of Two-Dimensional Materials: A Review.

Two-dimensional (2D) materials are widely used in microelectronic devices due to their excellent optical, electrical, and mechanical properties. The performance and reliability of microelectronic devices based 2D materials are affected by heat dissipation performance, which can be evaluated by studying the thermal conductivity of 2D materials. Currently, many theoretical and experimental methods have been developed to characterize the thermal conductivity of 2D materials. In this paper, firstly, typical theoretical methods, such as molecular dynamics, phonon Boltzmann transport equation, and atomic Green’s function method, are introduced and compared. Then, experimental methods, such as suspended micro-bridge, 3ω, time-domain thermal reflectance and Raman methods, are systematically and critically reviewed. In addition, the physical factors affecting the thermal conductivity of 2D materials are discussed. At last, future prospects for both theoretical and experimental thermal conductivity characterization of 2D materials is given. This paper provides an in-depth understanding of the existing thermal conductivity measurement methods of 2D materials, which has guiding significance for the application of 2D materials in micro/nanodevices.

Morphology Analysis of Spontaneous Tin (Sn) Whisker Growth on Lead-Free Solder

Due to the transition of the electronics industry to lead-free solders, the issue of tin (Sn) whisker has become one of the most imperative issues that need to be resolved. Moreover, with the increasing demand for electronics miniaturization, Sn whisker growth is a severe threat to the reliability of microelectronic devices. Sn whisker is a conductive tin structure that grows spontaneously from tin finished surfaces, which can lead to well-documented system failures in electronics industries. Assessment of the Sn whisker growth is difficult because of the slow and unpredictable nature of the Sn whisker formation. This paper presents the results of morphology analysis of Sn whisker growth in terms of Sn whiskers shape, average density and maximum length of Sn whisker on Sn-Cu solder finished using scanning electron microscope (SEM). Micro-indentation test was used to accelerate the growth of Sn whisker at room temperature storage.

Microscale interfacial adhesion assessment in a multilayer by a miniaturised four-point bending test

Microscale techniques capable of selectively isolating and delaminating embedded multilayer interfaces in a stable manner have the potential to be powerful characterisation tools for improving the reliability of microelectronic devices. Here we propose an analytical approach to assess the steady-state strain energy release rate during the delamination of an embedded multilayer interface, initiated by our recently developed miniaturised four-point bending technique. Stable delamination of a SiN-GaAs interface was initiated via nanoindentation induced bending of microbridges that had been milled into the surface of an Al-SiN-GaAs multilayer using a focused ion beam. Analytical models quantify the strain energy released within a section of a microbridge using the load-displacement relation obtained during delamination. The models are validated by demonstrating their capacity to approximate the experimentally observed linear-elastic deformation of a reference microbridge under both three- and four-point bending. We find that deformation of the clamped-ends as well as indenter penetration of a microbridge contribute significantly to the total indenter displacement. We then show this can be accounted for through a combination of Euler–Bernoulli beam and Hertzian contact theory. A mean steady-state strain energy release rate of G¯SS=2.20±0.36Jm−2 is obtained for the SiN–GaAs interface.

Spontaneous Tin (Sn) Whisker Growth from Electroplated Tin and Lead-Free Tin Alloys Coatings: A Short Review

Since the environmental regulations of Reduction of Hazardous Substances (RoHS) directive came into effect in Europe and Asia on July 1, 2006, requiring the removal of any lead (Pb) content from the electronics industry, the issue of tin (Sn) whisker growth from pure Sn and SnPb-free alloys has become one of the most imperative issues that need to be resolved. Moreover, with the increasing demand for electronics miniaturization, Sn whisker growth is a severe threat to the reliability of microelectronic devices. Sn whiskers grow spontaneously from an electrodeposited tin coating on a copper substrate at room temperature, which can lead to well-documented system failures in electronics industries. The Sn whisker phenomenon unavoidably gives rise to troubles. This paper briefly reviews to better understand the fundamental properties of Sn whisker growth and at the same time discover the effective mitigation practices for whisker growth in green electronic devices. It is generally accepted that compressive stress generated from the growth of Cu6Sn5 intermetallic compound (IMC) is the primary driving force for Sn whisker growth during room temperature storage. It is, therefore, important to determine that the relationship between IMC growth and Sn whisker growth. Reduction of stress in the IMC layer can therefore reduce the driving force for whisker formation and be used as a means for whisker mitigation. To date, there are no successful methods that can suppress the growth of Sn whisker as efficient as Pb addition. It is hoped that the Sn whisker growth mechanisms are understood better in the future, with better measuring and monitoring methodologies and systems being developed, the real solutions may be eventually developed to eliminate or mitigate the Sn whisker problems of green reliability lead-free electronic assemblies.

Scratch induced thin film buckling for quantitative adhesion measurements

Adhesion of thin films is one of the most important factors determining reliability of microelectronic devices and semiconductor industry requires quantitative testing methods to effectively compare these interfaces. Several techniques have been developed over the last decades with scratch induced delamination being a rarely studied method. For compressively stressed films on rigid substrates scratching can cause buckling failure and by modeling the delaminations according to the Hutchinson and Suo model the adhesion can be determined quantitatively. Two different sample systems, a tungsten-titanium film on a silicate glass and a silicon nitride film on a silicate glass with a tungsten-titanium overlayer, have been tested using scratch loads in the range of 100–500 mN. This study demonstrates that the scratching resulted in buckles parallel to the scratch trace and triggered further spontaneous buckling. Using the dimensions of the induced buckles the interfacial adhesion energies were quantified. The adhesion energy of the tungsten‑titanium/silicate glass interface was measured to be 2.7 J/m2 and of the silicon nitride/silicate glass interface was 1.5 J/m2. The results illustrate that the scratch test can be utilized for quantitative adhesion testing of thin films and suggest that scratch induced delamination is a valuable addition to established adhesion measurement techniques.

Dissociation characteristics of proton release in a-SiO2 by first-principles theory

Radiation-induced interface traps are the essential defects affecting the reliability of microelectronic devices, and it is generally agreed that protons play a key role in the reaction that generates the traps. We thus perform first-principles calculations to investigate the reactions that possibly release protons in amorphous SiO2 (a-SiO2). Two fundamental mechanisms are explored, namely the dissociation of hydrogen molecules at positive oxygen vacancies and the dissociation of hydrogenated defects. The calculations show that there are high energy barriers for the singly hydrogenated vacancies to generate protons, and that the barrier for the doubly hydrogenated vacancy is relatively low. The calculations also show that the dissociation of hydrogen molecule at the dimer configuration has a lower energy barrier and a more stable product than the dissociation at the puckered configuration. The energy barrier of the dissociation at the dimer configuration can be as low as 0.58 eV, which ensures that the reaction can take place quickly at room temperature. The details of the reactions are investigated at the atomic scale to provide a microscopic insight into proton release in a-SiO2.

Quantitative Evaluation of Cobalt Disilicide/Si Interfacial Roughness

The formation of smooth, conformal cobalt disilicide (CoSi2) without facets or voids is critical for microelectronic device reliability owing to the ultra-shallow contact areas. Here we demonstrate the formation of smooth and conformal CoSi2 films by chemical vapor deposition (CVD) of cobalt nitride (CoxN) films on silicon (Si) or on silicon on insulator (SOI) substrates, followed by in-situ rapid thermal annealing (RTA) at 700°C. To reveal the CoSi2/Si interfacial morphology, we report a back-to-front sample preparation method, in which mechanical polishing, anisotropic tetramethylammonium hydroxide (TMAH) wet etching, hydrofluoric acid (HF) wet etching, and isotropic xenon difluoride (XeF2) dry etching are employed to remove the SOI substrate from the back side to expose the CoSi2/Si interface. This method offers a robust and reliable procedure for quantitative assessment of the CoSi2/Si interfacial roughness, as well as analytical support for advanced fabrication process development.

Microstructural Investigation of Pulse Electroplated Copper Trenches Deposited with Organic Additives

Preferential grain orientation of copper (Cu) vias is speculated to result in a decrease in stresses in elastically anisotropic Cu. On the other hand, highly twinned Cu microstructures are known to increase their electromigration resistance and mechanical properties, without significantly degrading electrical performance [1,2]. Therefore, the optimal manipulation of Cu via microstructure could enable the improvement of the reliability of microelectronic devices. In this study, the “tuning” of the microstructure of Cu trenches were achieved by varying the bath’s chemical composition in different trench aspect ratios. The organic additive system comprising of polyethylene glycol (PEG), bis-(sodium sulfopropyl)-disulfide (SPS), and janus green b (JGB) is commonly used in the electroplating of Cu into trenches and higher aspect ratio through-silicon vias (TSV) for microelectronics [3,4]. In this study, copper was pulse-electrochemically deposited (PED) into 500 nm deep trenches of various widths to evaluate the impact of aspect ratio on the evolution of copper microstructure. Trench aspect ratios of 0.25, 1, 2, and 2.78 were investigated. The organic additive concentrations in the PED bath were also adjusted to examine their influence on the Cu microstructure. By metallurgical sample preparation and the focused ion beam (FIB) technique, the sample cross-sections of the Cu filled trenches were revealed for microstructural analysis using electron backscattering diffraction (EBSD). From the EBSD data, the grain orientation and twin boundary distribution of the deposited Cu microstructure were analyzed.

Morphological stability of Pt coatings deposited on Cr substrates

The morphological stability of coatings is an important factor for the reliability of microelectronic devices operating at elevated temperature. The focus of this work was to characterise and explain the coating degradation mechanisms of Pt–Cr coatings and thereby to find ways of extending their operating temperature range. Platinum coatings on chromium are shown to be morphologically stable up to 800°C; at higher temperatures degradation is observed. Scanning electron microscopy of coated specimens with a systematic variation in both coating thickness and annealing temperature shows that significant grain-boundary grooving and agglomeration can occur. This has important implications for the reliability of microelectronic devices operating at elevated temperatures.

Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100nm near the transistors and 1000nm away from the transistors and near the solder bumps. In such BEOL stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers.This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data.

Steady-state low thermal resistance characterization apparatus: The bulk thermal tester.

The reliability of microelectronic devices is largely dependent on electronic packaging, which includes heat removal. The appropriate packaging design therefore necessitates precise knowledge of the relevant material properties, including thermal resistance and thermal conductivity. Thin materials and high conductivity layers make their thermal characterization challenging. A steady state measurement technique is presented and evaluated with the purpose to characterize samples with a thermal resistance below 100 mm(2) K/W. It is based on the heat flow meter bar approach made up by two copper blocks and relies exclusively on temperature measurements from thermocouples. The importance of thermocouple calibration is emphasized in order to obtain accurate temperature readings. An in depth error analysis, based on Gaussian error propagation, is carried out. An error sensitivity analysis highlights the importance of the precise knowledge of the thermal interface materials required for the measurements. Reference measurements on Mo samples reveal a measurement uncertainty in the range of 5% and most accurate measurements are obtained at high heat fluxes. Measurement techniques for homogeneous bulk samples, layered materials, and protruding cavity samples are discussed. Ultimately, a comprehensive overview of a steady state thermal characterization technique is provided, evaluating the accuracy of sample measurements with thermal resistances well below state of the art setups. Accurate characterization of materials used in heat removal applications, such as electronic packaging, will enable more efficient designs and ultimately contribute to energy savings.

Controlling kinetics of heterogeneous sol–gel solution for high-performance adhesive hybrid films

The strength of bonding at epoxy/SiO2 interface and its susceptibility to environmental degradation have profound impact on the lifetime and reliability of microelectronic devices. The incorporation of hybrid film at epoxy/SiO2 interfaces has been shown to alleviate this challenge, but the working time to produce these highly-adherent hybrid films on silicon has been limited to ~10 min. In this work we demonstrate that, by lowering sol–gel aging temperature to 5 °C, the processing window for producing highly-adherent hybrid films on silicon can be extended to more than 6 h. In addition to the extended processing time, an Arrhenius type relationship between sol–gel aging temperature and the optimal sol–gel aging time was observed, with an overall sol–gel reaction activation energy of approximately 2.03 eV/atom that includes both hydrolysis and polycondensation. The enhanced interfacial adhesion was explained in terms of the graded hybrid film structure as determined by X-ray photoelectron spectroscopy depth profiling. The work has significant implications for the successful integration of hybrid film strategy in device packaging technologies. Fracture energy of epoxy/hybrid-film/SiO2 structures with films prepared at different sol–gel aging times and temperatures. Black, red and blue curves show fracture energy as a function of sol-gel aging time for solutions aged at 25, 15 and 5 °C respectively. Grey dashed line indicates Gc = 60 J/m2 while orange dot-dash line represents the adhesion of epoxy/SiO2 interface in the absence of the hybrid film.